Ferroelectric Transistor Gate Stack for Low Power Operation
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Solution Overview
Problem
Oxide semiconductor transistors have limited applications due to high threshold voltage and insufficient on-current, restricting their use in low power devices, primarily because of the thick gate insulation layer and high gate and drain voltages.
Innovation Solution
Incorporating a ferroelectric material layer between the gate structure and internal electrode to create a negative capacitance effect, which amplifies the gate voltage, increases on-current, and allows for a thinner gate insulation layer without compromising low leakage current performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate insulation layer is used to maintain low leakage current, then leakage current is reduced, but on-current is limited and threshold voltage increases
Solution Approach 1:
A ferroelectric layer is introduced as an intermediary between the gate electrode and the gate insulation layer. This ferroelectric layer generates a negative capacitance effect that amplifies the gate voltage, enabling the transistor to achieve high on-current with a thinner gate insulation layer while maintaining low leakage current performance
Solution Approach 2:
The invention changes the electrical parameters of the gate structure by incorporating the ferroelectric layer, which modifies the voltage-capacitance relationship. This allows the gate insulation layer thickness to be reduced from conventional thick values to thinner values (e.g., 50-150 nm) while still achieving the desired low leakage current through the voltage amplification effect
2Reliability
If a thick gate insulation layer is used to keep low leakage current, then leakage current is reduced, but gate voltage and drain voltage become too high for low power devices
Solution Approach 1:
The ferroelectric layer acts as a voltage amplifier intermediary, converting a small applied gate voltage into a larger effective voltage across the channel. This voltage amplification reduces the required gate and drain voltages for low power operation while maintaining the low leakage current achieved with the optimized gate insulation layer thickness
3Use of energy by moving object
If the gate insulation layer is made thinner to reduce voltage requirements, then power consumption is reduced, but leakage current increases
Solution Approach 1:
The ferroelectric layer serves as a protective intermediary that enables the use of thinner gate insulation layers. Through its negative capacitance effect, it compensates for the reduced insulation thickness by amplifying the gate voltage, thus maintaining low leakage current even with the thinner layer structure
Solution Approach 2:
The gate stack is designed as a composite structure combining the ferroelectric layer with the gate insulation layer. This composite configuration leverages the voltage amplification property of the ferroelectric material to offset the reduced insulation effect of the thinner gate insulation layer, achieving both low power consumption and low leakage current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances on-current and reduces sub-threshold swing, enabling the transistor to operate in low power devices with reduced gate and drain voltages, expanding its application field.
Implementation Method 1
a ferroelectric material layer is disposed between the gate structure and the internal electrode for forming a negative capacitance effect
Data Source
AI summary
A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.