Ferroelectric Field Effect Transistor with Hafnium Zirconium Oxide Gate Dielectric
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Solution Overview
Problem
Current ferroelectric field effect transistor (FeFET) devices face challenges in achieving reduced size and improved electrical properties such as desirable subthreshold swing (SS) and high on/off current ratio (ION/IOFF).
Innovation Solution
The FeFET device incorporates a 3D transistor structure with a channel body and a gate dielectric layer made of crystalline hafnium zirconium oxide, ranging in thickness from 2 nm to 5 nm, which is electrically isolated from the drain and source electrodes, enhancing the on/off current ratio and reducing subthreshold swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate dielectric layer thickness is reduced to achieve smaller device size, then the device dimensions are reduced, but the electrical control and on/off current ratio deteriorate
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of a first gate dielectric layer (e.g., silicon oxide) and a second gate dielectric layer (e.g., hafnium oxide or hafnium zirconium oxide). This composite structure enables thinner overall thickness while maintaining superior electrical control through the high-k properties of the second layer, resolving the contradiction between device miniaturization and electrical performance
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing high-k materials (hafnium oxide with k≈25-30, or hafnium zirconium oxide with adjustable k values) in the second gate dielectric layer. This parameter change allows the gate dielectric layer to be thinner while maintaining or improving electrical control, enabling device size reduction without sacrificing reliability
2Ease of manufacture
If conventional gate dielectric materials are used to simplify manufacturing, then the manufacturing process is easier, but the on/off current ratio and subthreshold swing performance are insufficient
Solution Approach 1:
The patent uses a composite gate dielectric structure where the first layer (conventional material like silicon oxide) provides interface quality and the second layer (high-k material like hafnium oxide) provides superior electrical control. This composite approach achieves high on/off current ratios (>10^6) and good subthreshold swing while remaining compatible with existing CMOS manufacturing processes
Solution Approach 2:
The patent modifies the dielectric constant parameter by incorporating high-k materials, achieving on/off current ratios exceeding 10^6 and subthreshold swing values approaching 60 mV/dec. The sequential deposition process allows standard manufacturing techniques to be used while achieving enhanced electrical performance
3Productivity
If the gate dielectric layer is made thinner to increase transistor density, then the device density increases, but the leakage current increases and on/off ratio decreases
Solution Approach 1:
The patent employs a composite gate dielectric structure where the high-k second layer (hafnium oxide or hafnium zirconium oxide) provides superior barrier properties that suppress leakage current even at reduced thicknesses. This enables higher transistor density with maintained or improved on/off current ratios, directly addressing the leakage current issue
Solution Approach 2:
By changing the dielectric constant parameter to higher values through high-k materials, the patent achieves better leakage suppression at thinner thicknesses. The high-k materials provide higher breakdown fields and better charge retention, enabling transistor density increases without proportional increases in leakage current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FeFET device achieves an on/off current ratio greater than 5×10^4 and subthreshold swing values below 60 mV/dec, suitable for ultra-low power consumption and high-speed logic computing applications.
Implementation Method 1
a ferroelectric material having a high-k dielectric constant is capable of switching its polarization to exhibit a negative capacitance upon application of a critical voltage
Implementation Method 2
switching its polarization to exhibit a negative capacitance
Implementation Method 3
a ferroelectric material having a high-k dielectric constant is capable of switching its polarization
Data Source
AI summary
A ferroelectric field effect transistor (FeFET) device includes a semiconductor substrate and a 3D transistor. The 3D transistor includes drain and source electrodes; a channel structure that includes a channel body and a gate dielectric layer; and a gate electrode that is disposed on the gate dielectric layer and that is electrically isolated from the drain and source electrodes. The channel body is disposed between and connected to the drain and source electrodes. The gate dielectric layer covers the channel body, is made of crystalline hafnium zirconium oxide, and has a thickness ranging from 2 nm to 5 nm. The FeFET device has an on/off current ratio that is greater than 5×104.