Ferroelectric Transistors With Interface Switching Modulation Layers
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Solution Overview
Problem
Ferroelectric devices face challenges in achieving a wide memory window to represent multiple bit states due to parasitic charge trapping, which limits their ability to store additional polarization states and requires high programming voltages, making them less suitable for modern low-power and fast memory applications.
Innovation Solution
Incorporating interface switching modulation (ISM) layers with hafnium oxide, silicon oxide, and titanium oxide to enhance ferroelectric devices, creating material dipoles that interact constructively with ferroelectric dipoles, thereby increasing the memory window and allowing for reliable operation with more than two-bit capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional ferroelectric devices are used, then they can maintain logical/memory state without power, but they suffer from narrow memory window and require high programming voltages
Solution Approach 1:
An interface switching modulation (ISM) layer is introduced between the ferroelectric layer and the electrode. This ISM layer acts as an intermediary that modulates the interface properties, enabling wider memory window and lower programming voltages by controlling the interaction between the ferroelectric material and the electrode
Solution Approach 2:
The patent changes the physical and chemical parameters of the interface between the ferroelectric layer and electrode by introducing the ISM layer. This includes modifying the interface dipole moment, work function, and electrical properties, which results in improved memory window and reduced programming voltage requirements
2Quantity of substance
If ferroelectric devices are used for multi-bit storage, then storage capacity increases, but parasitic charge trapping limits the ability to represent multiple bit states
Solution Approach 1:
The patent converts the harmful parasitic charge trapping effect into a beneficial mechanism. The ISM layer is designed to utilize trapped charges to create a compensating field that enhances the memory window, transforming the previously harmful charge trapping into a useful mechanism for achieving multi-bit storage states
Solution Approach 2:
The patent employs a composite structure consisting of the ferroelectric layer combined with the ISM layer. This composite material system leverages the complementary properties of both layers, where the ISM layer's response to trapped charges enhances the overall device performance and enables reliable multi-bit storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ISM layers overcompensate for parasitic charge trapping, resulting in a larger memory window that enables the storage of multiple bit states with lower operating voltages, making ferroelectric devices more suitable for low-power, high-speed applications like neural networks and in-memory computing.
Implementation Method 1
ferroelectric devices that include interface switching modulation (ISM) layers that enhance the operation of the devices. Specifically, ferroelectric transistors and tunnel junction devices include ISM layers such that material dipoles reinforce internal electric fields
Implementation Method 2
A ferroelectric device is a logic/memory device that can maintain its logical/memory state even when power is removed. The ferroelectric material may act like a dielectric that 'remembers' or stores electric fields to which it has been exposed. In a ferroelectric device, a persistent dipole (or so-called 'domain') may be formed within the gate dielectric itself
Data Source
AI summary
An enhanced ferroelectric transistor may include Interface switching modulation (ISM) layers along with a ferroelectric layer in the gate of the transistor to increase a memory window while maintaining relatively low operating voltages. The enhanced ferroelectric transistor may be implemented as a memory device storing more than two bits of information in each memory cell. An enhanced ferroelectric tunnel junction device may include ISM layers and a ferroelectric layer to amplify the tunneling barriers in the device. The ISM layers may form material dipoles that add to the effect of ferroelectric dipoles in the ferroelectric material.