Ferroelectric Transistor Memory Cell for On-Chip Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory cells for logic chips, such as 6T and 8T SRAM, consume large areas and require high programming voltages, limiting their integration density and efficiency on-chip, while denser nonvolatile memory elements and DRAM require high refresh power, making them difficult to integrate on a logic die.
Innovation Solution
A memory cell integrating a ferroelectric transistor and a selection transistor with a ferroelectric capacitor, allowing for programming using voltages not exceeding logic supply voltages (e.g., 1.8 V) and longer pulse widths, enabling denser on-chip memory with reduced power consumption and integration complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 6T or 8T SRAM is used for on-chip memory, then memory functionality is achieved, but area consumption increases
Solution Approach 1:
The patent merges the memory storage function and selection function into a single integrated structure. The ferroelectric transistor serves both as the storage element (replacing separate storage transistor and capacitor) and as the selection device, eliminating the need for separate 6T or 8T transistor arrays and reducing cell area while maintaining full memory functionality
Solution Approach 2:
The patent extracts the selection function from the traditional SRAM architecture and integrates it directly into the storage transistor structure. By making the storage transistor itself selectable through gate control, the design removes redundant selection transistors and simplifies the overall cell structure, achieving higher density
2Area of stationary object
If denser NVM elements or DRAM are used, then memory density increases, but programming voltage or refresh power requirements increase
Solution Approach 1:
The patent changes the operational parameters of the memory cell by using ferroelectric material properties (hysteresis loop characteristics) to enable storage at standard logic supply voltages. The ferroelectric capacitor's ability to maintain polarization states without continuous power allows dense storage without the high refresh power of DRAM or high programming voltages of traditional NVM
Solution Approach 2:
The ferroelectric transistor structure serves multiple functions simultaneously: it acts as the storage element, the selection device, and operates at standard logic voltages. This multi-functionality eliminates the need for separate high-voltage programming circuits and refresh mechanisms, reducing overall power consumption while achieving high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a dense, programmable on-chip memory that occupies less space, uses lower voltages, and reduces power consumption, making it suitable for integration into logic devices like neuromorphic computing and CPUs, with improved retention times and reduced noise margins.
Implementation Method 1
The ferroelectric capacitor includes ferroelectric material(s)
Data Source
AI summary
A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.