Ferroelectric Transistor Structure for Scaled Memory State Switching
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining performance, particularly in the integration of transistors and interconnect structures, where the shrinking geometry and increasing functional density require innovative manufacturing methods to enhance transistor performance and memory cell functionality.
Innovation Solution
The integration of a ferroelectric layer with a hole supply layer between the channel layer and the gate electrode in the second transistor, along with a unique manufacturing process that includes damascene gate formation, metal layer deposition, and specific etching techniques, allows for improved performance by enabling the writing and erasing of memory cell states, enhancing the overall performance of the second transistor and memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then productivity and cost efficiency are improved, but transistor performance and memory cell functionality deteriorate
Solution Approach 1:
The patent introduces a hole supply layer with specific properties (higher electron trap density than the channel layer) localized between the second gate electrode and channel layer. This local structural modification with distinct material properties enables the transistor to maintain performance functionality despite overall geometry scaling, resolving the contradiction between size reduction and performance maintenance.
Solution Approach 2:
The patent employs a composite structure combining multiple layers including ferroelectric layer, channel layer, hole supply layer, and metal layer with different functional properties. This composite material approach allows the transistor to achieve both scaled-down dimensions and maintained performance by leveraging the synergistic effects of different material layers, particularly the hole supply layer's electron trapping capability.
2Area of stationary object
If geometry size is decreased to increase functional density, then area occupied is reduced, but memory cell state writing and erasing capability deteriorates
Solution Approach 1:
The patent adds a vertical dimension to the transistor structure by introducing the hole supply layer between the gate electrode and channel layer. This vertical stacking approach enables memory cell functionality in a scaled-down planar footprint, allowing the device to maintain writing and erasing capabilities while occupying reduced chip area through three-dimensional structural optimization.
3Device complexity
If conventional transistor structure is used in scaled-down geometry, then manufacturing simplicity is maintained, but performance and functionality are insufficient
Solution Approach 1:
The patent segments the transistor structure into distinct functional layers including the hole supply layer, channel layer, ferroelectric layer, and metal layer. This segmentation allows each layer to be optimized for its specific function while maintaining a relatively simple overall manufacturing process, resolving the contradiction between structural simplicity and performance requirements in scaled-down devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient writing and erasing of memory cell states, improving the performance of the second transistor and memory cell, and addresses the challenges of scaling down ICs by maintaining performance and functionality in smaller geometries.
Implementation Method 1
An electron trap density of the hole supply layer is higher than an electron trap density of the channel layer
Implementation Method 2
The integration of a ferroelectric layer with a hole supply layer between the channel layer and the gate electrode
Data Source
AI summary
A transistor includes a first gate electrode, a ferroelectric layer, a channel layer, a second gate electrode, and a hole supply layer. The ferroelectric layer is disposed over the first gate electrode. The channel layer is disposed on the ferroelectric layer. The second gate electrode is disposed over the channel layer. The hole supply layer is located between the second gate electrode and the channel layer. An electron trap density of the hole supply layer is higher than an electron trap density of the channel layer.