Ferroelectric Transistor Fabrication Without Plasma Channel Damage
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in forming ferroelectric layers for transistors, as plasma deposition can damage the channel layer, leading to defects and degraded performance due to gate leakage, especially when the channel width is large and defects are not fully recoverable by annealing.
Innovation Solution
The formation of ferroelectric layers using a non-plasma deposition process, such as ALD or CVD, to reduce plasma-induced defects, followed by subsequent annealing to remove other process-related defects, ensuring a substantially defect-free channel layer and improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma deposition is used to form ferroelectric layers, then deposition efficiency is improved, but channel layer defects increase and transistor performance degrades
Solution Approach 1:
The harmful plasma treatment step is extracted and removed from the deposition process. The patent specifically eliminates plasma exposure during ferroelectric layer formation, using only non-plasma deposition methods to avoid channel layer damage while maintaining deposition efficiency.
Solution Approach 2:
The patent replaces plasma-based deposition with non-plasma deposition methods such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). This substitution eliminates the harmful mechanical/chemical action of plasma on the channel layer while still achieving effective ferroelectric layer formation.
2Power
If channel width is increased, then transistor drive current is improved, but plasma-induced defects become more significant and are not fully recoverable by annealing
Solution Approach 1:
The patent replaces plasma deposition with non-plasma deposition methods (ALD, CVD) to avoid introducing defects in the first place. This prevention approach is particularly important for wider channels where defects cannot be fully removed by subsequent annealing processes.
Solution Approach 2:
The patent performs preliminary protection of the channel layer by using non-plasma deposition from the outset, preventing defect formation before it occurs. This preliminary action avoids the need for defect recovery through annealing, which is insufficient for plasma-induced defects in wide-channel devices.
3Ease of manufacture
If conventional plasma deposition is used, then ferroelectric layer formation is achieved, but gate leakage increases due to channel layer damage
Solution Approach 1:
The patent substitutes plasma deposition with non-plasma deposition methods (ALD, CVD) that do not damage the channel layer. This substitution maintains the ability to form high-quality ferroelectric layers while eliminating the gate leakage problem caused by plasma-induced channel damage.
Solution Approach 2:
The patent introduces non-plasma deposition processes as an intermediary method between the ferroelectric layer formation requirement and the channel layer protection requirement. This intermediary approach satisfies both needs without the harmful effects of plasma exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces defects in the channel layer, prevents degradation of the current on/off ratio, and ensures the performance of the second transistor is maintained, even with larger channel widths, by avoiding plasma-induced damage during ferroelectric layer formation.
Implementation Method 1
The formation of ferroelectric layers using a non-plasma deposition process, such as ALD or CVD
Implementation Method 2
The formation of ferroelectric layers using a non-plasma deposition process, such as ALD or CVD
Implementation Method 3
followed by subsequent annealing to remove other process-related defects
Data Source
AI summary
A manufacturing method of a transistor includes at least the following steps. An insulating layer is provided. A source/drain material layer is formed on the insulating layer to cover top surface and sidewalls of the insulating layer. A portion of the source/drain material layer is removed until the insulating layer is exposed, so as to form a source region and a drain region respectively on two opposite sidewalls of the insulating layer. A channel layer is deposited on the insulating layer, the source region, and the drain region. A ferroelectric layer is formed over the channel layer through a non-plasma deposition process. A gate electrode is formed on the ferroelectric layer. The gate electrode, the ferroelectric layer, and the channel layer are patterned to expose at least a portion of the insulating layer, at least a portion of the source region, and at least a portion of the drain region.