Ferroelectric Transistor Ring Structures for Memory Integration
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Solution Overview
Problem
Current ferroelectric transistors face challenges in scalability for increasing levels of integration in memory arrays, limiting their performance and efficiency in data storage.
Innovation Solution
The integration of ferroelectric transistors with rings of ferroelectric material extending around vertically-extending wordline structures, combined with specific materials and configurations such as MFMIS and MFIS structures, to enhance scalability and functionality in memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ferroelectric transistors are used in memory arrays, then basic memory functionality is achieved, but scalability to ever-increasing levels of integration is limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically-stacked FeFET architectures. The ferroelectric layer is positioned between the gate electrode and channel region in a vertical stacking configuration, enabling increased integration density by utilizing the third dimension (vertical direction) rather than only horizontal plane expansion.
Solution Approach 2:
The patent implements nested structural configurations where the ferroelectric layer is positioned between the gate electrode and channel region, creating a compact multi-layer stack. Source and drain regions are vertically stacked above and below the channel region, with insulating layers and conductive interconnects nested between levels, maximizing space utilization and integration density.
2Reliability
If ferroelectric material is integrated into transistor structures, then nonvolatile memory capability is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the ferroelectric layer early in the fabrication sequence, before subsequent metallization and interconnect formation steps. The vertically-stacked structure is established upfront, allowing later processes to build upon this foundation without requiring complex reconfiguration, thereby simplifying overall manufacturing despite the advanced architecture.
Solution Approach 2:
The patent utilizes parameter changes in the ferroelectric material properties, specifically exploiting the electric field-induced polarization switching between distinct stable states. This physical property enables nonvolatile data storage through reversible polarization transitions, achieving reliable data retention through material property optimization rather than complex structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables scalable and efficient memory arrays with improved data storage capabilities, maintaining memory states even without power, and allowing for higher integration levels.
Implementation Method 1
the different polarization modes may be characterized by, for example, different threshold voltages (Vt) or by different channel conductivities for a selected operating voltage. The ferroelectric polarization mode of a FeFET may remain in the absence of power (at least for a measurable duration).
Data Source
AI summary
Some embodiments include a ferroelectric transistor having a conductive gate structure, a first ring extending around the conductive gate structure and a second ring extending around the first ring. The first ring includes ferroelectric material. The second ring includes insulative material. A mass of channel material is outward of the second ring. Some embodiments include integrated assemblies and methods of forming integrated assemblies.