Ferroelectric Transistor Stacking for Memory Density
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Solution Overview
Problem
Ferroelectric memory cells with a 1T type structure face challenges in achieving high integration and density due to the large plane area required for each memory cell, as unselected cells can be overwritten during data writing, and existing solutions with selection transistors for each cell are inefficient.
Innovation Solution
A semiconductor storage apparatus is designed with a first transistor having a ferroelectric film and a second transistor with source or drain regions on an activation layer, allowing controlled application of an electric field to the ferroelectric film, reducing the plane area and preventing data overwrite in unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a 1T type structure is used for ferroelectric memory cells, then the circuit can consume less power and enable high-speed operation, but the plane area of each memory cell becomes large making high integration and high density difficult to achieve
Solution Approach 1:
The patent merges the selection transistor and the memory cell transistor into a single integrated structure. The first transistor serves dual functions as both the memory cell element and the selection transistor, eliminating the need for separate selection transistors and reducing the overall plane area while maintaining low power consumption characteristics
Solution Approach 2:
The first transistor with ferroelectric film is designed to perform multiple functions simultaneously: it acts as the memory cell for data storage and as the selection transistor for controlling data access. This multi-functionality reduces the number of components needed and achieves higher integration density
2Reliability
If a selection transistor is provided for each memory cell to prevent data overwrite, then data integrity is improved, but the plane area of each memory cell becomes large
Solution Approach 1:
The selection function and memory cell function are merged into the single first transistor structure. The ferroelectric film's ability to maintain polarization state provides inherent selection capability, eliminating the need for separate selection transistors while preventing data overwrite in unselected cells
Solution Approach 2:
The patent applies different functional qualities to different parts of the first transistor: the ferroelectric film provides non-volatile storage and selection capability locally, while the channel region provides data storage. This localized functional differentiation enables the single transistor to perform both selection and storage functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high integration and density of memory cells by controlling the electric field applied to the ferroelectric film, preventing data interference and reducing the plane area, thus improving storage density.
Implementation Method 1
a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions
Implementation Method 2
a ferroelectric memory that stores information using the direction of remanent polarization of a ferroelectric
Implementation Method 3
it is possible to control the presence or absence of occurrence of an electric field with respect to the ferroelectric film of the first transistor by the second transistor provided on the first transistor
Data Source
AI summary
To provide a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment in which memory cells are highly integrated and highly densified. A semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.