Ferroelectric Gate Stack for Tunnel MOSFET Sub-threshold Swing

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Solution Overview

Problem

Conventional Tunnel Field-Effect Transistors (TFETs) face limitations in achieving fast switching speeds due to high sub-threshold swing values, which restrict further scaling of operational voltage and threshold voltage, as the current mechanism is governed by band-to-band tunneling that quickly increases beyond initial low switching efficiency.

Innovation Solution

Incorporating a ferroelectric layer in the gate stack of TFETs, which includes a high-k dielectric layer, a diffusion barrier, and a conductive electrode, to enhance the sub-threshold swing by modifying the transport mechanism and reducing equivalent capacitance, thereby maintaining low switching speeds over a wider range of current increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If band-to-band tunneling mechanism is used in TFET, then low initial sub-threshold swing is achieved, but sub-threshold swing quickly increases at higher voltages

Engineering Contradiction:
Improvesub-threshold swing controlVSAvoidswitching speed
Core Design Contradiction:
Manufacturing precisionVSEase of operation

Solution Approach 1:

The patent introduces a ferroelectric layer in the gate stack that fundamentally changes the electrical characteristics of the device. The ferroelectric material provides a negative capacitance effect that modifies the sub-threshold swing parameter, enabling it to remain low across a wider voltage range. This parameter change allows the TFET to maintain fast switching characteristics beyond the initial turn-on region.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The gate stack is constructed as a composite structure incorporating a ferroelectric layer combined with conventional gate dielectric materials. This composite approach leverages the unique properties of ferroelectric materials (negative capacitance, high permittivity) while maintaining the structural framework of traditional MOSFET gate stacks, achieving improved sub-threshold swing characteristics without complete redesign.

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If conventional MOS device structure is used, then simple fabrication is maintained, but sub-threshold swing is limited to about 60 mV/decade

Engineering Contradiction:
Improvefabrication simplicityVSAvoidsub-threshold swing
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The gate dielectric stack is segmented into multiple functional layers, including a conventional gate dielectric layer and an additional ferroelectric layer. This segmentation allows each layer to perform its specific function - the conventional layer provides basic insulation and interface quality, while the ferroelectric layer provides negative capacitance for improved sub-threshold swing. The segmented structure can be integrated into existing fabrication processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ferroelectric layer acts as an intermediary element between the gate electrode and the channel. It mediates the electrical interaction by providing negative capacitance that amplifies the gate voltage effect on the channel, thereby improving sub-threshold swing without requiring fundamental changes to the device operation or fabrication methodology.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If operational voltage is scaled down, then power consumption is reduced, but switching speed becomes limited by diffusion transport

Engineering Contradiction:
Improvepower consumptionVSAvoidswitching speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent replaces the diffusion-based transport mechanism with a tunneling-based mechanism enhanced by ferroelectric negative capacitance. Instead of relying on thermal diffusion of carriers (which limits switching speed at low voltages), the TFET uses quantum mechanical band-to-band tunneling that is accelerated by the ferroelectric field effect, enabling faster switching at reduced power consumption.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The introduction of a ferroelectric layer in the TFET gate stack significantly reduces sub-threshold swing values and extends the range of low switching efficiency, allowing for faster and more efficient transistor operation compared to conventional TFETs.

Implementation Method 1

Incorporating a ferroelectric layer in the gate stack of TFETs, which includes a high-k dielectric layer, a diffusion barrier, and a conductive electrode, to enhance the sub-threshold swing by modifying the transport mechanism

Methodology Applied
Scientific EffectFerroelectric effect:

Implementation Method 2

In a TFET, electron injection is governed by the band-to-band tunneling from the valence band of the source to the conduction band of the channel

Methodology Applied
Scientific EffectBand-to-band tunneling:

Implementation Method 3

forming a high-k gate dielectric over the semiconductor substrate

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS9768030B2Method for forming tunnel MOSFET with ferroelectric gate stack
Publication Date: 2017.09.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9768030B2 patent drawing
  • US9768030B2 patent drawing
  • US9768030B2 patent drawing

AI summary

A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.