Ferromagnetic-Core Inductor Packaging for Stress-Controlled Wafer Integration
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Solution Overview
Problem
The integration of multiple semiconductor devices in wafer-level packaging poses challenges for miniaturization, higher speed, and reduced transmission and insertion losses, requiring innovative packaging and assembling techniques to meet increasing demands.
Innovation Solution
The development of a semiconductor device manufacturing process involving a carrier with de-bonding layers, encapsulation of semiconductor dies with conductive and dielectric materials, and the formation of redistribution structures with ferromagnetic-core inductors, where the core is surrounded by a buffer and etch stop layer to manage mechanical stress and enhance manufacturing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are integrated in wafer-level packaging, then device density and functionality are improved, but manufacturing complexity and stress management become worsened
Solution Approach 1:
The packaging structure is segmented into multiple functional layers including carrier, de-bonding layer, encapsulant, buffer layer, etch stop layer, and core material layer. Each layer performs a specific function, allowing complex multi-device integration while managing stress and manufacturing complexity through modular design.
Solution Approach 2:
The patent employs a nested layered structure where the buffer layer is positioned between the core material layer and encapsulant, with the etch stop layer providing additional functional separation. This nested arrangement allows multiple semiconductor devices to be integrated within the wafer-level package while systematically managing mechanical stress and process complexity.
2Reliability
If higher speed and reduced transmission loss are achieved, then electrical performance is improved, but manufacturing precision and structural control requirements become worsened
Solution Approach 1:
The patent applies local quality by positioning specific functional layers at precise locations: the buffer layer is placed adjacent to the core material layer where stress management is critical, while the etch stop layer is positioned to control etching processes during manufacturing. This localized functional assignment enables high electrical performance through optimized signal transmission paths while maintaining manufacturability through controlled structural features at critical locations.
Solution Approach 2:
The de-bonding layer is pre-positioned between the carrier and encapsulant before final device integration. This preliminary action facilitates subsequent device attachment and stress management operations, enabling high-precision structural control during manufacturing while achieving the required electrical performance in the final assembled device.
3Volume of moving object
If miniaturization is pursued, then device size is reduced, but stress management and manufacturing yield become worsened
Solution Approach 1:
The patent employs thin film layers including the buffer layer and etch stop layer that provide flexible stress management capabilities in miniaturized devices. These thin functional layers can be precisely deposited and controlled during manufacturing, enabling device size reduction while maintaining stress balance and manufacturing yield through controlled film properties and thicknesses.
Solution Approach 2:
The patent uses composite material structures with multiple layers having different mechanical and electrical properties. The buffer layer, etch stop layer, encapsulant, and core material layer form a composite structure that manages stress in miniaturized devices while maintaining manufacturing yield. Each material is selected and positioned to optimize both size reduction and reliability in the final miniaturized semiconductor device.
Data Source
AI summary
A manufacturing method of a semiconductor device includes: forming a first dielectric layer on inductor traces, openings of the first dielectric layer exposing the inductor traces; disposing a buffer material on the first dielectric layer and the inductor traces in the openings; sequentially disposing an etch stop material and a ferromagnetic material on the buffer material; removing the ferromagnetic material from over the openings to form a core material layer covering a first area; removing the etch stop and buffer materials from the openings to form an etch stop layer and a buffer layer, where the etch stop and buffer layers cover a second area, the first area is smaller than and within the second area; forming a second dielectric layer on the first dielectric layer to embed the buffer, etch stop, and core material layers; and forming inductor vias extending through the first and second dielectric layers.