FET Air-Gap Fin Structure for Lower Parasitic Capacitance

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Solution Overview

Problem

Existing methods for reducing parasitic capacitance in field-effect transistors, such as FinFETs and GAA FETs, are inadequate when the number of active regions is reduced to two or less, as they fail to effectively introduce air gaps in the device structure.

Innovation Solution

The method involves forming dielectric fins adjacent to the outer semiconductor fins, creating outer air gaps and, in some cases, inner air gaps between merged epitaxial source/drain features, to increase the total number of air gaps and reduce parasitic capacitance, even when the number of semiconductor fins is reduced.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the number of semiconductor fins is reduced to two or less to increase device spacing, then parasitic capacitance reduction becomes more difficult, but device footprint is reduced

Engineering Contradiction:

Improvedevice footprintVSAvoidparasitic capacitance

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The device structure is segmented into multiple fins (first fin, second fin, third fin) with different configurations. The first and second fins have first epitaxial source/drain features, while the third fin has a second epitaxial source/drain feature. This segmentation allows creation of multiple air gaps between adjacent fins, ensuring sufficient parasitic capacitance reduction even when total fin count is low.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Air gaps are introduced in the vertical dimension between adjacent fins rather than only in the horizontal plane. The first air gap is formed between the first fin and second fin, and the second air gap is formed between the second fin and third fin, utilizing the vertical spacing to reduce parasitic capacitance without increasing horizontal footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of time

If air gaps are introduced to reduce parasitic capacitance, then RC delay is reduced, but device structure complexity increases

Engineering Contradiction:

ImproveRC delayVSAvoiddevice structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

Air gaps are selectively introduced only between specific adjacent fins (first fin-second fin, and second fin-third fin) rather than uniformly across all devices. This localized approach reduces parasitic capacitance where most needed while avoiding unnecessary structural complexity in other regions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Multiple fins (first fin, second fin, third fin) are merged into a single device structure with shared gate and substrate, allowing the creation of multiple air gaps within one device footprint. This combining approach achieves enhanced parasitic capacitance reduction without proportionally increasing overall device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12412777B2Reducing parasitic capacitance in field-effect transistors

Publication Date: 2025.09.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.