Two-Stage FET Amplifier Bias Feedback for High RF Linearity
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Solution Overview
Problem
FET amplifier circuits face inherent nonlinearity issues at radio frequencies, with existing linearization techniques being sensitive to bias variations, increasing noise factor, or requiring complex component counts and large circuit sizes, especially when aiming for integrated circuit implementation.
Innovation Solution
A two-stage FET amplifier with a feedback network in the second stage active bias circuit, utilizing a current mirror configuration and an RC feedback network to improve linearity by shifting the phase and level of signal intermodulation products, while maintaining balance between the current flowing in the current mirror and the amplifying FETs, and optimizing component values for frequency and size ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If source degeneration inductance with multiple FETs and tapped inductor is used for linearization, then linearity is improved, but circuit size increases significantly
Solution Approach 1:
The patent extracts the linearization function from the traditional source degeneration inductance approach and implements it through an active biasing circuit with feedback. This removes the need for multiple inductors including the tapped inductor, thereby maintaining linearity improvement while significantly reducing circuit size for integrated implementation.
Solution Approach 2:
The patent replaces the passive mechanical inductor-based source degeneration approach with an active electronic biasing circuit using FETs and feedback. This substitution eliminates the need for large inductors while achieving the same linearization effect, enabling compact integrated circuit design.
2Manufacturing precision
If tuned LC network is used for linearization in bipolar transistor, then linearity at specific frequency is improved, but bandwidth is reduced and it cannot be applied to FETs
Solution Approach 1:
The patent creates a universal linearization circuit based on active biasing with feedback that can be applied to both bipolar transistors and FETs. The circuit uses general electronic components (resistors, capacitors, transistors) rather than frequency-specific LC networks, enabling wideband operation and compatibility with different transistor types including FETs.
Solution Approach 2:
The patent employs dynamic active biasing with feedback control instead of static tuned LC networks. This allows the circuit to adapt to different frequencies and transistor types, providing wideband linearization performance that is not limited to specific resonant frequencies.
3Manufacturing precision
If multiple bias transistors and feedback sense circuit with resistors are used for distortion reduction, then linearity is improved, but periphery and die size increase
Solution Approach 1:
The patent merges the biasing function and linearization function into a single integrated active biasing circuit. By combining these functions and using impedance matching networks instead of separate resistor feedback circuits, the design achieves distortion reduction with minimized die size suitable for integrated circuits.
4Manufacturing precision
If impedance matching network is configured for nonlinearity cancellation, then intermodulation products are reduced, but output return loss deteriorates and design complexity increases
Solution Approach 1:
The patent employs feedback mechanisms in the active biasing circuit to automatically adjust and cancel nonlinear distortion products. This feedback-based approach simplifies the design process compared to manual impedance matching network configuration, reducing design complexity while maintaining effective intermodulation reduction.
Data Source
AI summary
A low-noise amplifier with high linearity has two common source FET amplifying stages, where the amplifier performance is linearized by use of a second stage active biasing circuit including a current mirror with a feedback network. The linearity improvement technique is employed on a 0.5-2 GHz flat gain amplifier. The improvement causes nodegradation to other RF parameters and allows for the amplifier circuit to be realized in a gallium arsenide microwave monolithic integrated circuit.