FET Array Gate Isolation for Dielectric Leakage Faults
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Solution Overview
Problem
Existing sensor arrays, such as those used in photodetectors, face issues with gate leakage currents due to defects in the dielectric material, which can affect the performance of other transistors in the array and increase complexity in control circuitry.
Innovation Solution
An array of field-effect transistors with a two-terminal current-limiting component, such as a diode, coupled to each gate electrode, which limits leakage current, preventing it from affecting other transistors and reducing noise through low-pass filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate electrodes of all transistors are connected in parallel to a common gate terminal, then the device complexity is reduced and ease of operation is improved, but leakage current from a defective transistor can affect other transistors in the array
Solution Approach 1:
The patent divides the gate electrode connections into segments by inserting individual current-limiting components between each gate electrode and the common gate terminal. This segmentation isolates leakage current to the defective transistor while maintaining the overall parallel connection structure for simplified control.
Solution Approach 2:
The current-limiting component acts as an intermediary element between the gate electrode and the common gate terminal. It mediates the electrical connection by allowing normal operation current to pass while blocking leakage current from affecting other transistors, thus resolving the contradiction between simplified control and reliability.
2Device complexity
If no current-limiting component is used, then the device complexity is minimized, but leakage current can flow freely and affect the performance of other transistors
Solution Approach 1:
The patent converts the potentially harmful leakage current into a controlled signal by using the current-limiting component to define a maximum leakage current level. This transforms the harmful effect into a predictable, limited phenomenon that does not compromise the overall array performance.
Solution Approach 2:
The current-limiting component serves as an intermediary that blocks the harmful leakage current while maintaining the electrical connection for normal operation. It mediates between the need for simple circuit structure and the need to prevent harmful current flow.
3Reliability
If current-limiting components are added to each gate electrode, then leakage current is limited and reliability is improved, but the device complexity increases
Solution Approach 1:
The patent applies current-limiting protection locally at each gate electrode connection point rather than implementing a complex global protection scheme. This local quality approach maintains reliability by protecting each transistor individually while keeping the overall structure relatively simple through repetition of the same basic element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively isolates affected transistors, maintaining the performance of the array by limiting leakage current and reducing noise, thus enhancing the reliability and stability of the sensor array.
Implementation Method 1
a respective two-terminal current-limiting component is coupled to each gate electrode such that, in the event that a defect in the dielectric material of a particular field-effect transistor allows a leakage current to flow between the channel and gate electrode of that field-effect transistor, the respective two-terminal current-limiting component limits the magnitude of the leakage current
Implementation Method 2
a gate electrode separated from the channel by a dielectric material configured to inhibit a flow of electrical current between the channel and gate electrode
Data Source
Figure 1
Figure 2a~2c
Figure 3
AI summary
An apparatus comprising an array of field-effect transistors, each field-effect transistor comprising a channel, source and drain electrodes configured to enable a flow of electrical current through the channel, and a gate electrode configured to enable the flow of electrical current to be varied, the gate electrode separated from the channel by a dielectric material configured to inhibit a flow of electrical current between the channel and gate electrode, wherein the gate electrode of each field-effect transistor is connected in parallel to the gate electrodes of the other field-effect transistors in the array, and wherein a respective two-terminal current-limiting component is coupled to each gate electrode such that, in the event that a defect in the dielectric material of a particular field-effect transistor allows a leakage current to flow between the channel and gate electrode of that field-effect transistor, the respective two-terminal current-limiting component limits the magnitude of the leakage current so that the other field-effect transistors in the array are substantially unaffected by the leakage current.