Backside Source-Drain Via Layout for FET Power Delivery
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Solution Overview
Problem
Current methods for power delivery to transistors, such as through-silicon-via middle (TSVM) connections and buried power rails, require silicon area and can negatively affect transistor performance, while direct backside connections (BSC) are difficult to integrate and may degrade mechanical stress.
Innovation Solution
A method involving the formation of a recess through a shallow trench isolation (STI) layer to create a via that connects the source and/or drain structure to the backside of the substrate, allowing for a larger contact surface and preserving mechanical stress, without the need for sacrificial dielectric plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If through-silicon-via middle (TSVM) connections or buried power rails are used to contact BS-PDN to transistors, then power delivery is enabled, but silicon area is consumed and transistor performance is degraded
Solution Approach 1:
The patent transitions from planar contact methods (TSVM, buried power rails) to a 3D approach by forming vias through the substrate thickness dimension. The recess etched through the substrate and filled with conductive material creates a vertical connection path that delivers power from the backside without consuming lateral silicon area, thus resolving the area penalty inherent in conventional methods.
Solution Approach 2:
Instead of contacting the source/drain structure from the front side or using intermediate layers, the patent inverts the approach by creating direct contact from the backside of the substrate. The recess is etched through the substrate to expose the source/drain structure, and conductive material is deposited to form a direct electrical connection, eliminating the need for TSVM or buried power rails.
2Ease of manufacture
If direct backside connection (BSC) is implemented using sacrificial dielectric plugs, then contact is enabled, but integration difficulty increases and mechanical stress is reduced
Solution Approach 1:
The patent removes the sacrificial dielectric plug step entirely from the process. Instead of forming plugs, depositing metal, and removing the sacrificial material, the method directly etches a recess through the substrate and fills it with conductive material. This extraction of the sacrificial plug step simplifies the integration process and reduces device complexity while maintaining the direct backside connection functionality.
3Ease of manufacture
If conventional BSC designs are used, then direct contact is achieved, but mechanical stress in transistors is reduced leading to performance degradation
Solution Approach 1:
The patent applies local quality by positioning the recess and conductive material contact precisely at the source/drain region without affecting the channel structure. The contact is formed locally at the backside through the recess, allowing direct electrical connection while preserving the mechanical stress characteristics of the transistor channel, thus avoiding the performance degradation associated with conventional BSC methods.
Data Source
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AI summary
The present disclosure relates to a method of fabricating a field-effect transistor, FET, structure, and to a FET structure obtainable by said method. The method comprises the steps of: forming a first fin structure (11) on a first side of a substrate (10), wherein the first fin structure (11) extends along a channel direction, and wherein the first fin structure comprises at least one first channel (12); forming a shallow trench isolation, STI, layer (13) on the first side of the substrate (10), wherein the STI layer (13) is arranged on opposite sides of the first fin structure (11); forming a first source and/or drain structure (21) along the first fin structure (11), wherein the first source and/or drain structure (21) electrically contacts the at least one first channel (12); etching a recess (25) from a second side of the substrate (10), which is opposite to the first side, wherein the recess (25) passes through a section of the STI layer (13), and wherein the recess (25) reaches the first source and/or drain structure (11); and filling the recess (25) with an electrically conductive material to form a via (26), wherein the via (26) is in contact with the first source and/or drain structure (21).