Ferroelectric FET Charge Trapping Band Misalignment
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Solution Overview
Problem
Ferroelectric field effect transistors (FeFETs) face challenges in achieving high remnant polarization and coercive field, which are crucial for memory devices, as existing structures often suffer from charge trapping and polarization loss due to misalignment of charge trapping bands with semiconductor channels.
Innovation Solution
Incorporating a charge-trapping-band misalignment layer between the semiconductor channel and the ferroelectric gate dielectric layer, shifting the charge trapping band to avoid electron trapping and maintain polarization, comprising a dielectric metal oxide layer that aligns with the external electrical field, thereby enhancing the energy gap and stability of the ferroelectric gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ferroelectric gate dielectric layer is used directly over the semiconductor channel, then the device structure is simple, but charge trapping occurs due to misalignment of the charge trapping band with the semiconductor channel, leading to polarization loss and reduced reliability
Solution Approach 1:
An interfacial layer is introduced as an intermediary between the semiconductor channel and the ferroelectric gate dielectric layer. This interfacial layer serves as a mediator that prevents direct interaction between the semiconductor channel and the charge trapping band of the ferroelectric material, thereby eliminating charge trapping while maintaining the ferroelectric properties. The interfacial layer acts as a buffer that resolves the band alignment mismatch without requiring complex restructuring of the entire gate dielectric system.
Solution Approach 2:
The gate dielectric system is segmented into multiple distinct layers: a semiconductor channel layer, an interfacial layer, and a ferroelectric gate dielectric layer. This segmentation allows each layer to perform its specific function independently - the semiconductor channel provides carrier transport, the interfacial layer prevents charge trapping, and the ferroelectric layer provides polarization storage. By dividing the system into functional segments, the patent achieves reliable polarization stability without compromising overall device simplicity.
2Ease of manufacture
If the charge trapping band is misaligned with the semiconductor channel, then manufacturing is simpler, but electron trapping occurs leading to reduced remnant polarization and coercive field
Solution Approach 1:
The interfacial layer serves as a mediator that eliminates the need for precise energy level alignment between the semiconductor channel and the ferroelectric gate dielectric layer. Instead of requiring complex processes to achieve perfect band alignment, the interfacial layer naturally prevents charge trapping by providing an energy barrier. This approach maintains manufacturing simplicity while achieving the precise alignment effect needed for high remnant polarization and coercive field.
Solution Approach 2:
The patent changes the energy level parameters of the gate dielectric system by introducing the interfacial layer with specific electronic properties. This parameter change - the introduction of an intermediate energy level structure - fundamentally alters the charge transport characteristics, preventing electron trapping without requiring complex manufacturing processes. The interfacial layer's energy level positioning creates an effective barrier that maintains high polarization stability.
3Duration of action of moving object
If no interfacial layer is used, then the device structure is simpler, but charge trapping leads to polarization loss and reduced endurance
Solution Approach 1:
The interfacial layer acts as a protective intermediary that prevents charge trapping events during repeated write/erase cycles. By blocking the direct interaction between electrons and the charge trapping band, the interfacial layer preserves polarization integrity over extended operation periods. This intermediary structure is essential for achieving high memory endurance, as it prevents the cumulative degradation that would otherwise occur during repeated switching operations.
Solution Approach 2:
The interfacial layer provides beforehand cushioning against charge trapping by establishing a protective barrier before any charge trapping can occur. This preventive measure is in place from the initial device formation, cushioning against potential polarization loss during subsequent operation. The interfacial layer absorbs or deflects potential harmful interactions between electrons and the ferroelectric charge trapping band, ensuring long-term polarization stability and high endurance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high remnant polarization and coercive field, preventing charge trapping and ensuring greater endurance and stability of the ferroelectric field effect transistors by offsetting the energy level of the charge trapping band from the Fermi level, thus improving the performance and reliability of memory devices.
Implementation Method 1
an energy level of the charge trapping band during an on-state is offset from an energy level of an energy band of minority charge carriers of the semiconductor channel
Implementation Method 2
A ferroelectric material is a material that may have spontaneous nonzero electrical polarization (i.e., non-zero total electrical dipole moment) when the external electrical field is zero. The spontaneous electrical polarization may be reversed by a strong external electric field applied in the opposite direction.
Implementation Method 3
The electrical polarization is dependent not only on the external electrical field at the time of measurement, but also on the history of the external electrical field, and thus, has a hysteresis loop.
Implementation Method 4
comprising a dielectric metal oxide layer that aligns with the external electrical field, thereby enhancing the energy gap and stability of the ferroelectric gate dielectric layer
Data Source
AI summary
A ferroelectric field effect transistor includes a semiconductor substrate that contains a semiconductor channel that extends between a source region and a drain region. A ferroelectric gate dielectric layer is disposed over the semiconductor channel, and includes a ferroelectric material having a charge trapping band including electronic states generated by interfacial traps of the ferroelectric material. A gate electrode is located on the ferroelectric gate dielectric layer, and is configured to provide an on-state and an off-state for the ferroelectric field effect transistor through application of an on-voltage and an off-voltage, respectively, from a gate bias circuit. An energy level of the charge trapping band during the on-state is offset from an energy level of minority charge carriers of the semiconductor channel. Charge trapping in the ferroelectric material is avoided during operation of the ferroelectric field effect transistor, thereby increasing the endurance of the ferroelectric field effect transistor.