Bias Circuit for FET Transconductance Stability
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Solution Overview
Problem
Conventional bias circuits for field-effect transistors (FETs) suffer from performance degradation due to variations in power supply voltage, especially when using short-channel FETs, as they result in significant changes in transconductance (g m ) due to drain-induced barrier lowering (DIBL).
Innovation Solution
A bias circuit with two parallel current paths, each containing two amplifying elements, where one path includes diode-connected FETs and the other does not, configured to maintain comparable voltage drops across all FETs, thereby minimizing the impact of power supply voltage variations on transconductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional bias circuits are used with short-channel FETs, then the circuit can be constructed with modern short-channel devices, but the transconductance varies significantly with power supply voltage due to drain-induced barrier lowering
Solution Approach 1:
The patent changes the circuit topology parameters by introducing a specific configuration with two parallel current paths, where one path contains two diode-connected FETs and the other path contains two non-diode-connected FETs. This topological parameter change creates a bias circuit that compensates for DIBL effects in short-channel FETs, maintaining transconductance stability while being compatible with modern short-channel devices.
2Stability of the object's composition
If diode-connected FETs are used in bias circuits, then the voltage drops across FETs become more comparable, but the circuit complexity increases
Solution Approach 1:
The patent segments the bias circuit into two parallel current paths with distinct FET connection configurations. One path uses diode-connected FETs while the other uses non-diode-connected FETs. This segmentation allows each path to contribute differently to the overall bias generation, creating comparable voltage drops across all FETs while managing complexity through modular parallel structure.
Data Source
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AI summary
A bias circuit for biasing a field effect transistor (FET) to provide a transconductance (gm) that is substantially unaffected by power supply voltage variations. In one embodiment the circuit includes two parallel current paths, each including two amplifying elements such as FETs, the FETs in one of the paths both being diode-connected, and the FETs in the other path not being diode-connected. Variations in the power supply voltage result in comparable changes in the voltage drops across all four FETs, and drain-induced barrier lowering (DIBL) results in relatively small changes in gm with changes in power supply voltage.