Voltage-Controlled FET Biasing Circuits for Low-Distortion Attenuation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing voltage controlled circuits, particularly those using FETs, face challenges in minimizing distortion and noise, especially when employing buffer amplifiers, as they often fail to provide substantial improvements in linearity and attenuation, leading to issues with harmonic distortion and intermodulation distortion.
Innovation Solution
The implementation of a voltage controlled resistor circuit with a feedback network and an amplifier, such as a voltage follower, which isolates the feedback resistors from the drain terminal, effectively reducing distortion by ensuring that control voltage does not leak into the output, and using specific FET configurations like depletion mode and enhancement mode devices to achieve improved linearity and attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a buffer amplifier is used in voltage controlled circuits with FETs, then isolation between control and output is improved, but distortion and noise are not substantially reduced
Solution Approach 1:
The patent implements feedback networks that feed a portion of the output signal back to the input, creating negative feedback loops that reduce distortion and improve linearity. The feedback circuits are specifically designed to counteract the nonlinear characteristics of FETs, thereby reducing harmonic distortion without requiring complex buffer amplifier stages.
Solution Approach 2:
The patent utilizes the inherent characteristics of enhancement mode FETs and depletion mode FETs by changing their operating parameters through specific biasing schemes. By adjusting gate-source voltages and drain currents to optimal values, the circuits achieve improved linearity and reduced distortion without adding complex buffer amplifier stages, thus resolving the contradiction between distortion reduction and circuit complexity.
2Device complexity
If feedback networks are connected directly to FET drain terminals, then circuit simplicity is maintained, but control voltage leaks into output and distortion increases
Solution Approach 1:
The patent introduces operational amplifiers as intermediary elements between the FET drain terminals and the feedback networks. These op-amps act as buffer stages that isolate the control voltage from the output while maintaining the feedback function. The intermediary amplifiers prevent direct connection issues without significantly increasing overall circuit complexity, as they provide high input impedance and low output impedance characteristics.
3Manufacturing precision
If enhancement mode FETs are used instead of depletion mode FETs, then linearity and attenuation are improved, but circuit design complexity increases
Solution Approach 1:
The patent exploits the superior linearity characteristics of enhancement mode FETs by implementing specific biasing schemes that operate these devices in their most linear regions. The design includes carefully selected gate-source voltages and drain currents that maximize the linear operating range of enhancement mode FETs, thereby achieving improved linearity and attenuation performance without requiring overly complex circuit topologies.
Data Source
AI summary
A number of biasing circuits for amplifiers including voltage controlled amplifier is presented. Also a number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.