Main-Auxiliary FET Branch Topology for RF Harmonic Cancellation
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Solution Overview
Problem
Field-effect transistors (FETs) in switches introduce signal distortions due to harmonics, which affect the linearity of radio-frequency (RF) signals in wireless devices, limiting the performance of RF switching systems.
Innovation Solution
A circuit assembly with a main-auxiliary branch configuration, where the main path and auxiliary path are connected in parallel or series, with distinct gate bias networks to bias the FETs in strong and weak inversion regions, respectively, to generate distortions that cancel each other out, improving linearity by reducing third-order harmonics and intermodulation products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FETs are used as switches in RF circuits, then switching function is achieved, but signal linearity deteriorates due to harmonic distortions
Solution Approach 1:
The single FET switch is segmented into two parallel paths: a main path containing a first FET and an auxiliary path containing a second FET. Each path independently processes the RF signal, allowing the auxiliary path to generate opposite-phase distortions that cancel the main path distortions, thereby maintaining switching function while reducing harmonic content
Solution Approach 2:
The invention converts the harmful harmonic distortions generated by FETs into a beneficial cancellation mechanism. By biasing the auxiliary FET in weak inversion region, it generates third-order harmonics and intermodulation products that are opposite in phase to those from the main FET, transforming the harmful nonlinearity into a linearity-improving effect
2Productivity
If FETs operate in strong inversion region, then switching performance is improved, but nonlinearity increases
Solution Approach 1:
Different inversion regions are assigned to different FETs based on their functional roles. The main FET operates in strong inversion region to provide excellent switching performance with low on-resistance, while the auxiliary FET operates in weak inversion region to generate opposite-phase distortions, creating localized functional optimization in each path
3Device complexity
If a single FET configuration is used, then device complexity is low, but linearity is poor
Solution Approach 1:
The switch is segmented into two parallel FET configurations with separate gate bias networks. This segmentation allows independent optimization of each FET's operating point and distortion characteristics, achieving superior linearity through destructive interference of harmonics while maintaining manageable device complexity
Solution Approach 2:
The auxiliary FET path acts as a feedback mechanism that senses and counteracts the distortions generated by the main FET. By configuring the auxiliary path to generate opposite-phase third-order harmonics and intermodulation products, the system creates automatic distortion cancellation that improves linearity without requiring external feedback control
Data Source
AI summary
Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.