Buried Power Rail Under FET Source/Drain for Higher Chip Density
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Solution Overview
Problem
The challenge in modern integrated chips is to increase device density without degrading performance, as scaling down device features leads to increased capacitance and resistance-capacitance delay, and embedding power rails within the substrate decreases device density and adds design complexity.
Innovation Solution
The solution involves burying power rails within the semiconductor substrate directly under field-effect transistors (FETs) and using source/drain contacts to electrically couple them, reducing the number of conductive wires in the upper interconnect structure and decreasing design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device features are scaled down to increase device density, then device density increases, but capacitance and resistance-capacitance delay increase degrading performance
Solution Approach 1:
The patent moves power rails from the traditional planar interconnect layers into the vertical dimension by embedding them within the substrate. This dimensional transition allows power delivery without occupying lateral space that would interfere with densely packed FETs, thereby maintaining high device density while providing stable power supply to reduce RC delay effects.
Solution Approach 2:
The power rails are nested within the substrate structure itself, embedded between the front surface where FETs are located and the back surface of the substrate. This nesting approach integrates power delivery functionality within the existing substrate volume without adding external interconnect layers, thus maintaining device density while improving power delivery performance.
2Reliability
If power rails are embedded within the substrate, then power delivery is improved, but device density decreases and design complexity increases
Solution Approach 1:
By transitioning power rails from lateral interconnect layers to vertical embedding within the substrate, the patent eliminates the trade-off between power delivery and device density. The embedded power rails occupy the vertical space within the substrate thickness rather than lateral space, allowing maximum FET density on the front surface while maintaining effective power delivery pathways.
Solution Approach 2:
The substrate itself serves dual functions: as the mechanical support structure and as the medium containing the embedded power rails. This self-service approach integrates power delivery functionality into the substrate without requiring additional dedicated structures that would reduce device density or increase design complexity.
3Reliability
If power rails are embedded within the substrate, then power delivery is improved, but design complexity and processing challenges increase
Solution Approach 1:
The power rails are formed within the substrate before the FET fabrication process begins. This preliminary action establishes the power delivery infrastructure in advance, allowing subsequent FET processing to proceed without additional alignment steps for through-substrate vias, thereby reducing processing complexity while maintaining improved power delivery.
Solution Approach 2:
The patent extracts the power rail formation step from the complex sequence of through-substrate via alignment and interconnect formation steps. By forming power rails directly within the substrate as a separate preliminary process, it removes the need for subsequent via formation and alignment operations, thereby reducing design and processing complexity while maintaining effective power delivery.
Data Source
AI summary
The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a gate structure overlying a front-side surface of a first substrate. The first substrate has a back-side surface opposite the front-side surface. A first source/drain structure overlies the first substrate and is laterally adjacent to the grate structure. A power rail is embedded in the first substrate and directly underlies the first source/drain structure. A first source/drain contact continuously extends from the first source/drain structure to the power rail. The first source/drain contact electrically couples the first source/drain structure to the power rail.