FET Capacitor Circuit Architectures for Tunable RF Impedance Matching
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Solution Overview
Problem
Conventional RF front-end architectures in mobile handsets face challenges with impedance matching due to varying antenna load impedances, particularly in multi-band and wideband applications, where ferroelectric capacitors require high tuning bias voltages and are not easily integrated on-chip, and CMOS switched capacitor circuits occupy large IC area and are limited to sub-GHz frequencies.
Innovation Solution
The use of III-N FET capacitor structures with tunable capacitance, where the number of FET capacitor structures in an on-state is controlled by a tuning bias voltage, allowing for predictable MOS capacitance values and reduced tuning bias voltage range, enabling efficient impedance matching across a wide range of frequencies including GHz bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ferroelectric capacitors are used for tunable capacitance, then capacitance tuning range is achieved, but integration with on-chip circuitry becomes difficult and high tuning bias voltages are required
Solution Approach 1:
The patent changes the fundamental parameter of capacitance tuning from using ferroelectric materials to using MOS capacitor structures where capacitance is controlled by the inversion layer charge density. This allows standard CMOS fabrication processes to be used, achieving on-chip integration while maintaining tunable capacitance through voltage control of the MOS capacitance-cV characteristic.
Solution Approach 2:
The patent replaces the ferroelectric material-based capacitance tuning mechanism with an electric field-controlled MOS capacitor mechanism. Instead of relying on ferroelectric polarization switching, the invention uses the voltage-dependent depletion and inversion layers in MOS structures to achieve capacitance modulation, enabling compatibility with standard semiconductor fabrication.
2Adaptability or versatility
If ferroelectric capacitors are used for tunable capacitance, then capacitance tuning range is achieved, but tuning bias voltage becomes excessively high
Solution Approach 1:
The patent changes the voltage range required for capacitance tuning by using MOS capacitor structures that exhibit significant capacitance variation over low voltage ranges (0-5V). The MOS cV curve provides a natural capacitance modulation mechanism that operates efficiently at low bias voltages, eliminating the need for high voltage sources and reducing power consumption in portable devices.
3Ease of manufacture
If CMOS switched capacitor circuits are used for impedance matching, then integration is achieved, but IC area becomes large and frequency limit is sub-GHz
Solution Approach 1:
The patent changes the operating frequency capability by using III-N FET structures (GaN, AlN) that inherently support high-frequency operation up to GHz and beyond. These wide-bandgap semiconductor devices maintain their electrical characteristics at high frequencies, enabling RF impedance matching applications in the GHz range while maintaining compact on-chip integration.
4Adaptability or versatility
If analog C-V curves are used for capacitance tuning, then continuous capacitance variation is achieved, but noise and drift from bias voltage fluctuations increase
Solution Approach 1:
The patent employs dynamic control of MOS capacitor inversion layer charge density through bias voltage to achieve continuous capacitance variation. The MOS cV curve provides a smooth, continuous capacitance transition that can be precisely controlled by the bias voltage, enabling continuous impedance matching while the well-defined physical mechanism reduces sensitivity to noise and drift.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a compact and efficient tunable capacitance circuit that effectively matches RF impedance across various frequencies, reducing power consumption and enabling integration of RF matching circuitry within the RFFE, while minimizing the impact of bias voltage noise and drift.
Implementation Method 1
The tunable capacitance comprises a MOS capacitance associated with each of the FET capacitor structures
Data Source
AI summary
Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.