2D FET Cell Layout for Thermal Dissipation
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Solution Overview
Problem
The linear arrangement of Field Effect Transistor (FET) cells leads to 'bunching' of thermal dissipation, resulting in high channel temperatures, which is not efficiently addressed in existing technologies.
Innovation Solution
The FET cells are arranged in a two-dimensional array with gate electrodes aligned vertically and horizontally, creating three sections that allow heat to dissipate over a larger unshared surface area, reducing source inductance and optimizing phase matching for maximum power and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If FET cells are arranged in a linear array, then the device structure is simple and easy to manufacture, but thermal dissipation is concentrated causing high channel temperatures
Solution Approach 1:
The patent transitions from a one-dimensional linear array arrangement to a two-dimensional distributed array arrangement of FET cells. This dimensional change allows heat to dissipate across a larger surface area in multiple directions, reducing thermal concentration and channel temperature while maintaining manufacturing feasibility through systematic layout patterns.
2Temperature
If FET cells are arranged in a two-dimensional array, then thermal dissipation is improved and channel temperature is reduced, but the device layout complexity increases
Solution Approach 1:
The patent divides the FET device into multiple discrete cells arranged in a two-dimensional array, with each cell containing segmented source, drain, and gate regions. This segmentation approach distributes thermal load across multiple independent units while organizing them in a systematic pattern that manages layout complexity through modular design.
3Length of stationary object
If FET cells are arranged in a linear array, then the vertical dimension is larger, but the thermal dissipation area is limited
Solution Approach 1:
The patent expands the thermal dissipation area by arranging FET cells in a two-dimensional array that utilizes both horizontal and vertical space efficiently. This layout increases the effective heat dissipation surface area without proportionally increasing the overall vertical dimension, as heat can now dissipate in multiple directions across the array rather than being constrained to a linear path.
Data Source
Figure 1
Figure 2A~4B
Figure 3A
AI summary
A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.