FET Channel Layer Atomic Structure for High Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability, performance, and integration density while maintaining low power consumption and multifunctionality, particularly in field effect transistors where electric characteristics need improvement.
Innovation Solution
The use of a channel layer with a two-dimensional atomic layer made of a first material, such as phosphorene, and source/drain layers made of a second material like graphene, connected by covalent bonds, enhances the electric characteristics of field effect transistors and semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor devices are used to increase integration density and complexity, then device functionality and performance are improved, but reliability and electric characteristics deteriorate
Solution Approach 1:
The patent changes the material parameters by using two-dimensional atomic layers (phosphorene channel layer with specific thickness, graphene source/drain layers) instead of conventional bulk materials. This parameter change enables high integration density while maintaining superior electric characteristics including high carrier mobility and low leakage current, thus resolving the contradiction between integration density and reliability
Solution Approach 2:
The patent employs composite material structure combining phosphorene (channel layer) with graphene (source/drain layers), connected by covalent bonds. This composite approach leverages the complementary properties of both materials: phosphorene provides appropriate bandgap for switching while graphene provides high conductivity for current transport, achieving both high integration density and excellent reliability
2Speed
If channel layer thickness is reduced to improve device performance, then electron and hole mobility are improved, but leakage current increases
Solution Approach 1:
The patent optimizes the thickness parameter of the phosphorene channel layer to a specific range (single atomic layer or few atomic layers) where quantum confinement effects enhance carrier mobility while the material's intrinsic bandgap properties maintain low leakage current. This precise parameter control resolves the contradiction between speed and energy loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved electric characteristics, including higher electron and hole mobility, lower leakage current, and increased integration density, enabling more efficient and high-performance semiconductor devices.
Implementation Method 1
the channel layer and the source/drain layer are connected to each other by covalent bonds between the first and second materials
Data Source
AI summary
A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.