FET Contact Resistance Reduction via Dummy Transistor Segmentation
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Solution Overview
Problem
The shrinking size of field effect transistors (FETs) leads to increased contact resistance due to reduced contact size, limiting circuit performance, and existing solutions like increasing contact size or material composition alterations have not been sufficiently effective within lithographic and design constraints.
Innovation Solution
Incorporating active and active dummy FETs into circuit designs to increase the number of contacts, thereby enhancing the total contact interface area and reducing resistance, while maintaining component size and pitch constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact size is increased to reduce contact resistance, then the contact resistance decreases, but the lithographic constraints and design constraints are violated
Solution Approach 1:
The invention divides the contact structure into multiple segments by introducing dummy FETs adjacent to the active FET. Each FET contributes its own source and drain contacts, effectively segmenting the current path into multiple parallel contact routes. This segmentation increases the total contact interface area without requiring each individual contact to exceed lithographic limits, thereby reducing overall contact resistance while maintaining manufacturability.
Solution Approach 2:
The invention merges the active FET with dummy FETs to form a composite structure where multiple FETs share common source or drain regions. This merging creates a combined contact structure where the total contact area is the sum of individual FET contacts, achieving reduced contact resistance through area aggregation without violating design constraints on individual component sizes.
2Reliability
If the contact size is increased to reduce contact resistance, then the contact resistance decreases, but the component size and pitch constraints are violated
Solution Approach 1:
Instead of enlarging a single contact beyond pitch constraints, the invention segments the contact function across multiple FET units. Each FET maintains its standard-sized contacts within pitch limits, but the parallel arrangement of multiple FETs collectively provides the equivalent of a larger contact area, achieving low resistance without exceeding component size constraints.
Solution Approach 2:
The invention transitions from increasing contact area in the planar dimension (which would violate pitch constraints) to achieving equivalent area by adding structures in the vertical dimension of circuit design - stacking multiple FETs in parallel. This dimensional shift allows area aggregation without lateral expansion, maintaining compliance with pitch and size constraints.
3Reliability
If more contacts are added to reduce resistance, then the total contact interface area increases, but the circuit capacitance increases which slows down switching
Solution Approach 1:
The invention applies local quality by strategically placing dummy FETs only at specific locations where contact resistance needs reduction, rather than uniformly increasing contacts throughout the circuit. The dummy FETs are positioned adjacent to active FETs in a controlled manner, providing localized resistance reduction without globally increasing capacitance. This selective application maintains switching speed by limiting the total added capacitance to only where necessary.
Data Source
AI summary
A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.