Semiconductor FET Layout With Cover Metal for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with finger-shaped electrodes, the arrangement of multiple FETs in the extending direction of electrodes can lead to increased gate resistance and parasitic capacitance between the drain electrode and gate wiring, resulting in deteriorated characteristics.
Innovation Solution
The semiconductor device incorporates a first and second transistor unit with specific electrode configurations, including a gate wiring and cover metal layers strategically positioned to suppress parasitic capacitance, with the cover metal layers potentially overlapping or in contact with the gate wiring to reduce gate-drain and gate-source parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple FETs are arranged in the extending direction of electrodes, then the device can handle higher current and power, but gate resistance increases and parasitic capacitance between drain electrode and gate wiring increases
Solution Approach 1:
A cover metal layer is introduced as an intermediary element between the drain electrode and gate wiring. This cover metal layer acts as a shield that reduces the parasitic capacitance formed between the drain electrode and gate wiring, thereby mitigating the harmful capacitive coupling effect while maintaining the multi-FET arrangement for high power handling
Solution Approach 2:
The patent utilizes the concept of converting the harmful parasitic capacitance into a beneficial shielding effect. By placing the cover metal layer (connected to source potential) between the drain and gate wiring, the originally harmful capacitive coupling is transformed into a controlled shielding arrangement that reduces interference and improves high-frequency characteristics
2Power
If multiple FETs are arranged in the extending direction of electrodes, then the device can handle higher current and power, but gate resistance increases
Solution Approach 1:
Instead of arranging FETs only in the planar extending direction, the patent introduces a vertical dimension by stacking cover metal layers above the substrate at different positions. This three-dimensional arrangement allows multiple FETs to be connected in parallel for high power handling while the vertical cover metal structure provides shielding without increasing gate resistance
3Object-affected harmful factors
If cover metal layers are placed between source electrode and gate wiring, then parasitic capacitance is suppressed, but device complexity increases
Solution Approach 1:
The cover metal layer is merged with existing electrode structures and combined with the gate wiring layout. Rather than adding completely separate components, the cover metal is integrated into the existing interconnect structure, forming a unified design that reduces parasitic capacitance without proportionally increasing device complexity
Data Source
AI summary
A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode electrically, and a second drain electrode, a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, and electrically connected to the first source electrode, and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, and electrically connected to the second source electrode.