Cross-Coupling Contact Formation in FET Gate Structures
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Solution Overview
Problem
Existing methods for forming self-aligned gate contacts and cross-coupling contacts in field-effect transistors often result in weak contacts due to over-thinning of the conductor and damage to semiconductor material during the etching process, particularly when forming cross-coupling contacts.
Innovation Solution
A method involving the formation of a gate structure with sidewall spacers and a dielectric cap, where a portion of the cap is removed to expose the gate electrode, and an amorphization process is applied to the sidewall spacer to increase its etch rate, allowing for precise exposure and connection of the gate electrode with the epitaxial semiconductor layer, enhancing the contact's thickness and area of contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric cap is removed to expose the gate electrode top surface for cross-coupling contact formation, then the contact can connect with the gate electrode, but the semiconductor material is exposed to the etching process which damages it
Solution Approach 1:
The patent segments the dielectric cap removal process by applying amorphization selectively to the sidewall spacer region rather than uniformly across the entire structure. This localized modification allows the etching process to selectively remove the dielectric cap only where needed for cross-coupling contact formation, while protecting the semiconductor material regions from etching damage.
Solution Approach 2:
The amorphization process creates local quality differentiation in the sidewall spacer, making only the portion adjacent to the gate electrode top surface more susceptible to etching. This localized property change enables precise control over where the dielectric cap is removed, ensuring exposure of the gate electrode for contact formation while maintaining protection of the semiconductor material.
2Manufacturing precision
If the conductor is thinned during polishing to planarize, then the surface is planarized, but the cross-coupling contact becomes weak
Solution Approach 1:
The patent applies amorphization to the sidewall spacer before the etching and contact formation processes. This preliminary modification ensures that when the dielectric cap is subsequently removed, the gate electrode top surface is exposed with adequate conductor thickness already preserved, preventing the need for excessive polishing that would weaken the cross-coupling contact.
3Manufacturing precision
If the amorphization process is applied to the sidewall spacer, then the etch rate is increased for precise exposure, but the process complexity increases
Solution Approach 1:
The patent changes the physical-chemical parameter of the sidewall spacer by applying an amorphization process, which modifies the material structure to increase etch rate. This parameter change enables precise exposure of the gate electrode top surface during dielectric cap removal, achieving the desired manufacturing precision through material property modification rather than complex process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach strengthens the self-aligned cross-coupling contacts by ensuring a direct and robust connection between the gate electrode and the epitaxial semiconductor layer, reducing the risk of semiconductor material damage and improving contact reliability.
Implementation Method 1
a portion of the sidewall spacer is modified with an amorphization process
Data Source
AI summary
Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A sidewall spacer is formed adjacent to a gate structure, a dielectric cap is formed over the gate structure and the sidewall spacer, and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. A first portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a portion of a top surface of a gate electrode of the gate structure. A portion of the sidewall spacer is modified with an amorphization process. The modified portion of the sidewall spacer and the underlying gate dielectric layer are removed to expose a portion of a sidewall of the gate electrode. A cross-coupling contact is formed that directly connects the portions of the sidewall and top surface of the gate electrode with the epitaxial semiconductor layer.