Parallel FET Current Sharing Circuit for SSPC Load Balancing
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Solution Overview
Problem
Solid state power controllers (SSPCs) connected in parallel face issues with capacitive load inrush and inductive load turn off, where FET devices can exceed their current ratings, leading to damage due to varying tolerances and unbalanced current distribution.
Innovation Solution
A load balancing circuit is implemented using multiple FET devices and bipolar devices connected in a specific configuration to share power and control current distribution, with resistors and a controller managing the operation to ensure balanced load sharing during transient states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple FET devices are connected in parallel to increase power capacity, then the power handling capability is improved, but the current distribution becomes unbalanced causing some FETs to exceed their current ratings
Solution Approach 1:
A current sharing circuit is introduced as an intermediary between the parallel FET devices and the load. This circuit includes resistors connected to the source terminals of the FETs and bipolar transistors that sense the current through these resistors. The bipolar transistors generate feedback signals that are applied to the gate terminals of the FETs, actively regulating the current distribution to prevent any single FET from exceeding its current rating while maintaining the overall power handling capability of the parallel configuration.
2Speed
If FET devices operate during transient states without current balancing, then the response speed is improved, but the current exceeds maximum ratings causing potential damage
Solution Approach 1:
The current sharing circuit implements continuous feedback control during transient states. Resistors connected to the source terminals of parallel FETs sense the instantaneous current through each device. These sensed currents are fed back through bipolar transistors to the gate terminals, dynamically adjusting the gate voltage to maintain balanced current distribution even during rapid transient conditions. This feedback mechanism ensures that no FET exceeds its maximum current rating while preserving the fast transient response capability needed for power control applications.
Data Source
AI summary
A load balancing circuit comprising a first power source, a first field effect transistor (FET) device having a drain terminal connected to the first power source and a source terminal connected to a first node, a first resistor connected to the first node and a second node, a load connected to the second node, a second FET device having a drain terminal connected to the first node and a source terminal connected to the second node, a third FET device having a collector terminal connected to a gate terminal of the first FET device and an emitter terminal connected to the second node, and a second resistor connected to a base terminal of the third FET device and the first node.