Self-Limited Current Field-Effect Transistor with Drain Channel Bottleneck
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Solution Overview
Problem
Power MOSFETs face a trade-off between high breakdown voltage and low output resistance, leading to high saturation currents that can cause rapid breakdown during short-circuit conditions, necessitating additional current limiters that increase system complexity and cost.
Innovation Solution
A field-effect transistor with self-limited current is designed, featuring a drain channel with a bottleneck structure that reduces saturation current by increasing output resistance only minimally, allowing for reduced power dissipation and elimination of external current limiters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-drain structure is used to reduce output resistance, then current supply capability is improved, but saturation current increases significantly
Solution Approach 1:
The patent applies local quality by creating a bottleneck structure specifically in the lower portion of the drain channel, while the upper portion maintains a wider cross-section. This localized geometric modification allows the channel to have different effective widths at different positions, achieving current limitation where needed while preserving overall current supply capability. The bottleneck region acts as a local constraint that reduces saturation current without significantly impacting the main current path.
2Strength
If breakdown voltage is increased by using thick and low-doped epitaxial layer, then voltage withstanding capability is improved, but output resistance increases
Solution Approach 1:
The patent segments the drain channel into two distinct portions: an upper portion with larger cross-section and a lower portion with smaller cross-section (bottleneck). This segmentation allows different regions to serve different functions - the upper portion maintains low resistance for current supply, while the lower portion provides geometric constraint for current limitation. The epitaxial layer is also segmented into first and second portions with different doping concentrations, enabling independent optimization of breakdown voltage and output resistance.
3Reliability
If saturation current is reduced to prevent breakdown during short-circuit, then reliability is improved, but current supply capability deteriorates
Solution Approach 1:
The patent creates a dynamic balance between current supply capability and saturation current limitation through the bottleneck structure. During normal operation, the upper portion of the drain channel with larger cross-section allows high current flow, maintaining power supply capability. During short-circuit conditions, the bottleneck in the lower portion becomes the limiting factor that prevents excessive saturation current, thereby protecting the device. This dynamic behavior adapts to different operating conditions automatically.
Data Source
AI summary
A field-effect transistor is integrated in a chip of semiconductor material of a first type of conductivity, which has a first main surface and a second main surface, opposite to each other. The transistor includes a plurality of body regions of a second type of conductivity, each one extending from the second main surface in the chip. A plurality of drain columns of the second type of conductivity are provided, each one extending from a body region towards the first main surface, at a pre-defined distance from the first main surface. A plurality of drain columns are defined in the chip, each one extending longitudinally between a pair of adjacent drain columns. The transistor includes a plurality of source regions of the first type of conductivity, each one of them extending from the second main surface in a body region; a plurality of channel areas are defined, each one in a body region between a source region of the body region and each drain channel adjacent to the body region. There are then provided a gate terminal extending over the cannel areas (with the gate terminal that is insulated from the second main surface), a source terminal contacting the source regions on the second main surface, and a drain terminal contacting the chip on the first main surface. In the transistor according to an embodiment of the invention, each drain channel includes a first residual portion having a first transversal width and a second prevalent portion having a second transversal width higher than the first transversal width.