Dual Gate Oxide Insulating Layers for FET Reliability
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Solution Overview
Problem
Existing field-effect transistors face limitations in etching selectivity between layers, restricting material choices for gate electrodes, semiconductor layers, and source/drain electrodes, which hampers the achievement of high reliability and performance, especially in thin-film transistors for display applications.
Innovation Solution
A field-effect transistor design incorporating a gate insulating layer with a first oxide containing Si and an alkaline earth metal, combined with a second paraelectric amorphous oxide layer containing a Group A element and a Group B element, such as Ga, Sc, or Y, allowing for varied etching rates and improved reliability by suppressing threshold voltage changes under bias temperature stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer gate insulating structure is used, then the device structure is simple, but etching selectivity between layers is limited and material choices are restricted
Solution Approach 1:
The gate insulating layer is divided into two distinct layers: a first gate insulating layer containing Si and an alkaline earth metal, and a second gate insulating layer containing a paraelectric amorphous oxide with a Group A element (alkaline earth metal) and a Group B element (Ga, Sc, Y, or lanthanoid). This segmentation enables different etching rates and material properties in each layer, providing etching selectivity and material choice flexibility without significantly increasing overall device complexity.
2Ease of manufacture
If conventional gate insulating materials are used, then the manufacturing process is simple, but threshold voltage stability under bias temperature stress is poor
Solution Approach 1:
The gate insulating layer employs a composite structure combining two different oxide materials with complementary properties. The first layer provides a stable base with Si and alkaline earth metal, while the second layer with paraelectric amorphous oxide containing Group A and Group B elements provides enhanced threshold voltage stability under bias temperature stress. This composite approach maintains manufacturability through standard sputtering or CVD processes while significantly improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the flexibility in material choices for field-effect transistors, leading to higher reliability and performance by reducing defects and variations in transistor characteristics, particularly in display elements like organic EL displays.
Implementation Method 1
containing a paraelectric amorphous oxide containing a Group A element which is an alkaline earth metal and a Group B element which is at least one selected from the group consisting of Ga, Sc, Y, and lanthanoid
Data Source
AI summary
A field-effect transistor including: a gate electrode, which is configured to apply gate voltage; a source electrode and a drain electrode, which are configured to take electric current out; a semiconductor layer, which is disposed to be adjacent to the source electrode and the drain electrode; and a gate insulating layer, which is disposed between the gate electrode and the semiconductor layer, wherein the gate insulating layer includes a first gate insulating layer containing a first oxide containing Si and an alkaline earth metal and a second gate insulating layer disposed to be in contact with the first gate insulating layer and containing a paraelectric amorphous oxide containing a Group A element which is an alkaline earth metal and a Group B element which is at least one selected from the group consisting of Ga, Sc, Y, and lanthanoid.