Semiconductor FET with Dummy Gate for Low-Resistance Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor structures, size scaling increases source/drain contact resistance and gate-to-source/drain contact capacitance, negatively impacting device performance.
Innovation Solution
The semiconductor structures incorporate a non-functioning second gate between the first and second source/drain regions, with the second source/drain contact being wider and closer to the second gate, reducing resistance and capacitance by optimizing the placement and design of source/drain contacts relative to the gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If size scaling is applied to reduce contact width for higher device density, then device density is improved, but source/drain contact resistance increases
Solution Approach 1:
The patent introduces a dummy gate structure that extends the contact region laterally beyond the active gate width. This dimensional extension in the lateral direction allows the source/drain contact to be wider than the active gate, thereby reducing contact resistance while maintaining the scaled-down device footprint for high density.
Solution Approach 2:
The dummy gate acts as an intermediary structure that provides additional contact area without affecting the active channel operation. It serves as a mediator between the conflicting requirements of small contact width (for density) and large contact width (for low resistance), allowing the contact to extend over the dummy gate region to achieve lower resistance.
2Productivity
If size scaling is applied to reduce separation distance between source/drain contacts and gates, then device density is improved, but gate-to-source/drain contact capacitance increases
Solution Approach 1:
The gate structure is segmented into an active gate portion and a dummy gate portion. The active gate controls the channel, while the dummy gate portion serves as an extension that provides contact area. This segmentation allows the contact to be positioned closer to the gate for high density while the capacitance is managed by the specific configuration of the dummy gate region.
Data Source
AI summary
Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.