FET Gate Work Function Tuning for Edge Leakage Suppression
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Solution Overview
Problem
Integrated circuit field effect transistors (FETs) fabricated on silicon-on-insulator (SOI) substrates face significant leakage issues due to the edge transistor phenomenon, where boron depletion at the edges of the FETs reduces the threshold voltage, leading to increased leakage current.
Innovation Solution
The solution involves modifying the gate structure of the FETs by forming extra P+ implant regions within the gate polysilicon structure overlying the edge transistors, thereby increasing the work function and threshold voltage of the edge transistors to match or exceed that of the central conduction channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional FET fabrication on SOI substrates is used, then high speed and low power consumption are achieved, but leakage current increases due to edge transistor phenomenon
Solution Approach 1:
The patent applies local quality by differentiating the gate work function between edge regions and central regions. The gate structure is engineered to have a higher work function at the edges compared to the center, creating spatially varying electrical characteristics that suppress edge leakage while preserving central channel performance.
Solution Approach 2:
The patent changes the work function parameter of the gate material as a function of position. By adjusting the gate composition or structure (e.g., using different metal alloys or doping levels) at edge regions versus central regions, the threshold voltage is modified locally to counteract the edge transistor effect and reduce leakage current.
2Object-generated harmful factors
If gate structure is modified to increase threshold voltage at edges, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The gate structure is segmented into edge regions and central regions with distinct work function characteristics. This segmentation allows independent optimization of each region's electrical properties, enabling leakage suppression at edges without adversely affecting the central channel's drive current and speed performance.
Solution Approach 2:
The gate structure introduces asymmetry in its electrical properties by creating a work function gradient across the channel width. The edge regions have different (higher) work function than the central region, breaking the symmetry of conventional uniform gates to specifically target and suppress the asymmetric edge transistor leakage phenomenon.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current by increasing the threshold voltage of the edge transistors, minimizing the difference in leakage current between the edge and central regions of the FET, and maintaining minimal impact on area and gate capacitance.
Implementation Method 1
forming extra P+ implant regions within the gate polysilicon structure overlying the edge transistors, thereby increasing the work function and threshold voltage of the edge transistors
Implementation Method 2
boron depletion at the edges of the FETs reduces the threshold voltage, leading to increased leakage current
Data Source
AI summary
FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ΦMF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ΦMF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.