FET Epitaxial Source-Drain Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional semiconductor devices face structural and operational deficiencies, including parasitic capacitors that affect operating speed due to the S2G distance, leading to reduced hole mobility and increased RC delay, and issues like stacking faults and cat ears in source/drain regions.
Innovation Solution
A semiconductor device with an epitaxial structure forming source or drain regions, featuring a laterally extending portion below the top surface and a vertically extending portion, where the position of the lateral end of the buried portion is controlled to optimize the S/D recess geometry, and the use of arsenic implantation and etching spacers to create undercut regions for improved stress distribution and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the spacer thickness is increased to reduce parasitic capacitance, then the S2G distance increases and parasitic capacitance decreases, but the S/D recess geometry becomes less optimized and manufacturing precision is affected
Solution Approach 1:
The source/drain structure is segmented into multiple portions: a first portion within the S/D recess, a second portion laterally extending below the substrate surface, and a third elevated portion above the substrate. This segmentation allows each portion to be optimized independently for different functions - the first portion for stress distribution, the second for minimizing parasitic capacitance by extending laterally beyond the gate, and the third for electrical contact
Solution Approach 2:
The source/drain structure extends in multiple spatial dimensions: vertically into the substrate recess, laterally beyond the gate structure footprint, and elevated above the substrate surface. This multi-dimensional configuration allows the source/drain to achieve both low parasitic capacitance (through lateral extension beyond gate) and proper stress distribution (through vertical recess formation) simultaneously
2Speed
If the source/drain is formed closer to the gate to reduce RC delay, then the operating speed improves, but the parasitic capacitance increases due to reduced S2G distance
Solution Approach 1:
The source/drain structure utilizes lateral extension beyond the gate footprint in the horizontal plane, rather than only vertical proximity, to minimize parasitic capacitance. The second portion extends laterally beyond the gate structure, achieving low capacitance coupling while the vertical positioning optimizes RC delay, resolving the contradiction through multi-dimensional spatial optimization
3Ease of manufacture
If conventional doping methods are used to form source and drain, then the process is simple, but stacking faults and cat ears defects occur in the source/drain regions
Solution Approach 1:
The conventional mechanical doping process is replaced with an epitaxial growth process where the source/drain structure is formed by depositing semiconductor material in the S/D recess and performing selective etching. This substitution eliminates the stacking faults and cat ears defects associated with doping while maintaining process feasibility through controlled epitaxial growth and etching steps
4Reliability
If the epitaxial structure extends laterally close to the gate, then hole mobility is enhanced through stress distribution, but the parasitic capacitance increases
Solution Approach 1:
The source/drain is segmented into portions with different lateral positions: the first portion within the recess provides stress for hole mobility, while the second portion extends laterally beyond the gate to minimize parasitic capacitance. This segmentation allows stress distribution for high mobility without excessive capacitance coupling
Solution Approach 2:
Different portions of the source/drain structure have different local qualities and positions: the first portion is positioned to provide compressive stress for hole mobility enhancement, while the second portion extends laterally beyond the gate footprint specifically to minimize parasitic capacitance. Each local region is optimized for its specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized geometry and stress distribution enhance hole mobility, reduce parasitic capacitance, and minimize defects like stacking faults and cat ears, resulting in improved operating speed and electrical characteristics.
Implementation Method 1
Since SiGe has a larger lattice constant than Si, an SiGe source/drain introduces a compressive stress in the channel of the FET, which increases the hole mobility in the channel
Implementation Method 2
implanting arsenic into the semiconductor substrate through the capping layer and using the gate structure as a mask to form an implanted region in the semiconductor substrate
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.