Merged Epitaxy Backside Cut for FET Source/Drain Isolation
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Solution Overview
Problem
As transistor dimensions shrink, merging of source and drain epitaxial features of neighboring transistors becomes difficult to avoid, leading to insufficient separation and undesirable parasitic capacitance, which is exacerbated by overetching into neighboring layers when transistors are separated by a long space.
Innovation Solution
The solution involves forming silicon features as seed layers during the formation of source and drain epitaxial features, which are intentionally merged prior to cutting, followed by backside processing to separate them without overetching into interlayer dielectric, using dielectric material to fill the openings, thereby ensuring sufficient separation and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase functional density, then production efficiency and cost are improved, but merging of source and drain epitaxial features becomes difficult to avoid, leading to insufficient separation and increased parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by forming seed layers (silicon features) before the epitaxial growth of source and drain regions. These seed layers are intentionally designed to control the merging behavior during subsequent processing steps, ensuring that even when transistors are closely spaced, the source and drain regions achieve proper separation after the cut and fill operation, thereby preventing excessive parasitic capacitance while maintaining high functional density
Solution Approach 2:
The patent introduces an intermediary structure (the seed layer made of silicon features) that mediates between the conflicting requirements of close transistor spacing and source/drain separation. This intermediary element controls the epitaxial growth and subsequent separation process, allowing the source and drain regions to be properly isolated even when transistors are densely packed, thus reducing parasitic capacitance without sacrificing productivity
2Object-generated harmful factors
If transistors are separated by a long space to avoid merging, then parasitic capacitance is reduced, but overetching into interlayer dielectric occurs during separation
Solution Approach 1:
The patent uses the seed layer as an intermediary that protects the interlayer dielectric during the separation process. The seed layer structure allows the etch to selectively remove material between source and drain regions without penetrating into the interlayer dielectric, thus achieving both good separation (reducing parasitic capacitance) and precise etching control (preventing overetching)
Solution Approach 2:
The patent applies preliminary action by pre-forming the seed layer structure that defines the separation geometry before the actual separation etch. This preliminary structure acts as a protective template that guides the etch process, ensuring that the separation is achieved with proper depth control and without damaging the interlayer dielectric
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively separates source and drain epitaxial features without overetching into neighboring layers, reducing parasitic capacitance and improving transistor performance.
Implementation Method 1
forming silicon features as seed layers during the formation of source and drain epitaxial features
Data Source
AI summary
A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.