Symmetric FET ESD Modeling Circuit Using Parasitic Bipolar Transistors
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Solution Overview
Problem
Current semiconductor integrated circuit modeling fails to effectively simulate electrostatic discharge (ESD) characteristics across various transistor polarities, limiting the accuracy of ESD protection in integrated circuits.
Innovation Solution
A modeling circuit for field-effect transistors is developed, incorporating a field-effect transistor, first and second current sources, and corresponding bipolar transistors, with substrate resistors, allowing for symmetric arrangement and operation based on electron-hole pairs generated in depletion layers, enabling simulation regardless of drain and source polarities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SPICE modeling is used for FETs, then general circuit simulation is achieved, but ESD characteristics cannot be accurately simulated
Solution Approach 1:
The FET is segmented into multiple functional components: a main FET channel, a depletion layer, and parasitic bipolar transistors. This segmentation allows the ESD protection mechanism to be modeled separately from the normal operation, enabling accurate ESD simulation while maintaining standard FET functionality through modular circuit elements.
Solution Approach 2:
The patent embeds a depletion layer with parasitic bipolar transistors inside the FET structure. The depletion layer is nested within the FET channel, and the bipolar transistors are nested within the depletion layer, creating a hierarchical model that captures ESD effects without replacing the entire FET model.
2Adaptability or versatility
If separate models are created for NMOS and PMOS ESD characteristics, then polarity-specific accuracy is achieved, but modeling time and complexity increase
Solution Approach 1:
The patent creates a universal ESD protection model that works for both NMOS and PMOS transistors. The parasitic bipolar transistor configuration automatically adapts to different polarities: for NMOS, the depletion layer forms between drain and substrate; for PMOS, it forms between source and substrate. This single model structure replaces the need for separate polarity-specific models, reducing analysis time while maintaining accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for accurate simulation of ESD characteristics in both gate-coupled NMOS and PMOS transistors, enhancing the analysis of ESD protection mechanisms and reducing analysis time, as it effectively models current flow under various voltage conditions.
Implementation Method 1
incorporating a field-effect transistor, first and second current sources, and corresponding bipolar transistors, with substrate resistors, allowing for symmetric arrangement and operation based on electron-hole pairs generated in depletion layers
Data Source
AI summary
A modeling circuit includes a field-effect transistor, a first current source, a first bipolar transistor, a second current source and a second bipolar transistor. The first bipolar transistor and the second bipolar transistor are parasitic bipolar transistors that are arranged symmetrically to each other. Therefore, the modeling circuit can be used in simulating the field effect transistors reflecting electrostatic-discharge characteristic regardless of the polarity of a source and a drain.