FET Layout Using Faker Contacts for Design Rule Compliance
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Solution Overview
Problem
The existing manufacturing methods for field effect transistors (FETs) face challenges in ensuring accurate electrical connections between the source, drain, and routing pattern regions, leading to design rule violations and inefficiencies in the verification process, particularly due to the limitations of current photolithography processes.
Innovation Solution
The method involves generating faker contact layers in the schematic layout to bypass electrical connection verification software constraints, allowing for the creation of a modified layout that ensures electrical connections are verified and compliant with design rules, ultimately facilitating the manufacturing of FETs without the need for additional interconnect metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional manufacturing methods are used without faker contact layers, then the manufacturing process is simpler, but electrical connection verification fails and design rules are violated
Solution Approach 1:
The patent introduces faker contact layers as intermediary elements in the schematic layout that act as mediators between the source/drain regions and the routing patterns. These fake contacts allow the verification software to detect electrical connections that would otherwise be missed due to photolithography process limitations, thereby enabling reliable verification without modifying the actual physical device structure.
Solution Approach 2:
The patent creates a copy of the contact structure in the form of faker contact layers within the schematic layout. These fake contacts are virtual representations that mimic the electrical connection function needed for verification purposes, allowing the design rule checker to properly verify electrical connections without requiring additional physical interconnect layers.
2Reliability
If additional interconnect metal layers are added to ensure electrical connections, then electrical connection reliability improves, but manufacturing cost increases
Solution Approach 1:
Instead of adding physical interconnect metal layers, the patent uses virtual faker contact layers in the schematic layout to represent and verify electrical connections. This copying approach allows complete electrical connection verification using existing manufacturing processes and materials, eliminating the need for additional expensive interconnect layers while maintaining connection reliability.
Solution Approach 2:
The faker contact layers serve as intermediary elements that enable electrical connection verification through software analysis rather than requiring additional physical metal layers. This intermediary approach allows the verification of source-to-drain and source-to-routing electrical connections using standard manufacturing processes, thereby reducing manufacturing costs while ensuring connection reliability.
3Manufacturing precision
If faker contact layers are used in schematic layout, then electrical connection verification succeeds and design rules are met, but the layout processing becomes more complex
Solution Approach 1:
The patent applies preliminary action by automatically generating faker contact layers during the layout creation process based on predefined rules and criteria. The system proactively identifies where fake contacts are needed to ensure electrical connection verification success, performing the verification preparation work before the actual manufacturing process begins, thereby ensuring design rule compliance without manual intervention.
Solution Approach 2:
The layout processing system performs self-service by automatically detecting the need for faker contact layers and generating them based on the electrical connection requirements. The system autonomously verifies electrical connections and adds the necessary fake contacts to the schematic layout without requiring external intervention, thereby maintaining design rule compliance while managing layout processing complexity through automation.
Data Source
AI summary
A field effect transistor (FET) including a substrate, a plurality of insulators, a gate stack, a first strained material, a second strained material, a first conducive via, a second conductive via, and a silicide layer. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are in the trenches. The gate stack is disposed over the semiconductor fins and on the insulators. The first strained material is located on one side of the gate stack and the second strained material is located on another side of the gate stack. The first conductive via is electrically connected to the first strained material and the second conductive via is electrically connected to the second strained material. The silicide layer contacts the first strained material and the first conductive via and contacts the second strained material and the second conductive via.