FET Field Plate and Booster Plate for Breakdown Voltage
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Solution Overview
Problem
Current field-effect transistors (FETs) face challenges in achieving high breakdown voltage and improved electrical performance, particularly at high drain voltage conditions, where the breakdown voltage is limited by surface electric fields around the drain region.
Innovation Solution
The design incorporates a drain extension region between the drain region and the gate structure, along with a field plate and a booster plate, which reduces the surface electric field and enhances the breakdown voltage by creating an electrical pathway for charge diffusion and boosting the surface electric field generated by the source region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional FET structure is used, then the device complexity is low, but the breakdown voltage is limited by surface electric fields around the drain region
Solution Approach 1:
The device is segmented into multiple functional regions including a drain extension region between the drain and gate, a field plate region extending over the drain extension, and a booster plate region underlying the field plate. This segmentation allows each region to independently manage electric field distribution, thereby increasing breakdown voltage while maintaining manageable structural complexity through modular design
Solution Approach 2:
The field plate extends in a lateral dimension over the drain extension region, and the booster plate is positioned in a vertical dimension underlying the field plate. This multi-dimensional arrangement creates an extended electrical pathway that dissipates surface electric fields more effectively, increasing breakdown voltage without proportionally increasing overall device footprint
2Reliability
If the surface electric field around the drain region is reduced, then the breakdown voltage increases, but the device area increases due to additional structures
Solution Approach 1:
The field plate and booster plate are merged into an integrated electric field management structure where the field plate sits directly over the booster plate. This merging allows the two components to work synergistically in reducing surface electric fields while minimizing the total area occupied compared to separate, distributed field management structures
Solution Approach 2:
The drain extension region acts as an intermediary structure between the drain and gate, providing a transition zone where the field plate and booster plate can effectively manage electric fields. This intermediary region allows for controlled electric field distribution that increases breakdown voltage without requiring excessive device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the breakdown voltage of the FET, enabling better electrical performance and handling of significant power levels, while maintaining efficient operation close to theoretical breakdown voltage.
Implementation Method 1
The booster plate enhances, or boosts, the surface electric field generated by the source region
Implementation Method 2
creating an electrical pathway for charge diffusion and boosting the surface electric field generated by the source region
Data Source
AI summary
A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.