FET Field Plate Vertical Dielectric Penetration
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Solution Overview
Problem
Existing field effect transistors (FETs) face design constraints due to the thickness of deposited dielectric layers and 3D surface topology, leading to limited ability to tailor electric field profiles for optimal breakdown and performance, especially at high frequencies, and are prone to metal cracking and thinning issues with field plates.
Innovation Solution
A transistor structure with a field plate that passes vertically into a dielectric structure and terminates at a predetermined finite distance above the semiconductor, decoupling its design from the thickness of deposited dielectric layers, allowing for independent control of the electric field and reducing metal cracking risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the field plate is deposited over dielectric spacer layers using lift-off processing, then the field plate can be formed after gate top formation, but the field plate design is constrained by the thickness of spacer layers and 3D surface topology
Solution Approach 1:
The field plate is extended vertically into the dielectric layer to create a three-dimensional structure. This vertical extension allows the field plate to reach closer to the gate edge while maintaining adequate spacing from the drain, thereby overcoming the limitations of planar deposition and enabling better electric field control without being constrained by spacer layer thickness.
2Ease of manufacture
If the field plate passes over 3D gate topology, then the field plate can be formed, but metal cracking and thinning occur
Solution Approach 1:
The field plate structure is segmented into multiple parts: a first portion extending from the gate edge toward the drain, and a second portion extending from the gate top toward the drain. This segmentation allows each portion to be independently optimized for thickness and position, reducing stress concentrations and preventing cracking while maintaining effective field control.
Solution Approach 2:
Different portions of the field plate are given different thicknesses and positions tailored to their specific functional requirements. The first portion has optimized thickness to control the electric field at the gate edge, while the second portion is positioned to provide additional field control without causing metal thinning over the 3D gate structure.
3Manufacturing precision
If the field plate distance from gate top is determined by spacer layer thickness, then the field profile can be controlled, but the design is limited by deposited dielectric layer thickness
Solution Approach 1:
The field plate design transitions from a two-dimensional planar structure to a three-dimensional structure with vertical extension into the dielectric layer. This allows precise control of the field plate-to-gate distance by adjusting the vertical penetration depth rather than being limited by horizontal spacer layer thickness, enabling superior field profile tailoring for optimal breakdown and high-frequency performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ability to tailor electric field profiles for improved breakdown and performance, particularly at high frequencies, while minimizing metal cracking and thinning issues, thereby optimizing FET performance.
Implementation Method 1
a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode and the drain electrode
Implementation Method 2
utilize field plates to lower the peak E-fields at the drain-edge of the gate electrode to enable higher breakdown capability
Data Source
AI summary
A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.