FET Gate Averaging Circuit for Low-Frequency Linear Resistance
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Solution Overview
Problem
Field-effect transistors (FETs) used as adjustable resistors face non-linear response issues due to varying voltages at the drain and source nodes, leading to distortion in signal representation when operating below a certain frequency, known as the corner frequency, where parasitic capacitances and isolation resistors fail to stabilize the resistance effectively.
Innovation Solution
The implementation of a circuit and method that includes an isolation resistor and parasitic capacitances to apply an average voltage of the drain and source nodes to the gate node, along with a control voltage, using amplifiers and resistors to maintain linear resistance stability up to the corner frequency, and optionally utilizing a backgate for further stabilization by applying the average voltage to both the gate and backgate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolation resistor and parasitic capacitances are used to stabilize the FET resistance, then the linear response is improved at high frequencies, but the linear response deteriorates below the corner frequency
Solution Approach 1:
An intermediary circuit is introduced between the drain and gate terminals, consisting of a voltage divider (first and second resistors) that samples the drain voltage and feeds back a portion to the gate. This intermediary mechanism compensates for the non-linear effects of the isolation resistor and parasitic capacitances at low frequencies, extending the linear response range below the corner frequency while maintaining high-frequency stability.
2Adaptability or versatility
If the FET is used as an adjustable resistor with control voltage at the gate, then the resistance is adjustable, but the response becomes non-linear due to varying drain and source voltages
Solution Approach 1:
A feedback mechanism is implemented where a portion of the drain voltage is fed back to the gate through a voltage divider network. This feedback compensates for the non-linear effects caused by varying drain and source voltages, maintaining a linear relationship between the control voltage and channel resistance across a wide voltage range, thereby preserving response linearity while maintaining resistance adjustability.
Solution Approach 2:
The invention changes the voltage parameter at the gate by superimposing the feedback voltage (derived from drain voltage) onto the control voltage. This parameter modification ensures that the gate voltage dynamically adjusts to compensate for drain and source voltage variations, maintaining linear resistance control throughout the operating range.
3Speed
If parasitic capacitances and isolation resistors are used for linearization, then high-frequency performance is improved, but the solution becomes ineffective below the corner frequency
Solution Approach 1:
The invention extends the linearization solution from the high-frequency domain to the low-frequency domain by introducing a additional feedback path through the voltage divider network. This dimensional extension of the solution approach allows the system to maintain linearization effectiveness across both high and low frequency ranges, overcoming the limitation of the corner frequency threshold.
Data Source
AI summary
Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.