FET Structure with Integrated Gate-Connected Diodes for Linearity
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Solution Overview
Problem
FET amplifiers face non-linear gate to source capacitance variations, which degrade their linear operation, particularly in RF applications, due to the hyperbolic tangent relationship between gate voltage and capacitance, requiring additional compensation to maintain linearity.
Innovation Solution
Each FET in a MMIC chip power amplifier is associated with its own linearizing diode, with the diode's anode in Schottky contact with the gate and cathode in ohmic contact with the drain, providing a large non-linear capacitance to balance out the gate to source capacitance variations, ensuring more linear amplifier operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a linearizing diode is added to the input of the FET amplifier, then the amplifier linearity is improved, but the device complexity increases
Solution Approach 1:
The patent merges the linearizing diode with the FET amplifier by integrating the diode structure directly into the amplifier circuit. The diode anode is connected to the FET gate and the cathode to the FET drain, combining two previously separate components (FET and linearizing diode) into a single integrated structure, thereby improving linearity without proportionally increasing overall device complexity
Solution Approach 2:
The integrated structure serves multiple functions: the FET provides amplification while the integrated diode provides linearization compensation. By making the diode an inherent part of the amplifier structure rather than a separate component, the system achieves multi-functionality within a single device, addressing both amplification and linearity requirements simultaneously
2Reliability
If the diode capacitance is increased to better compensate for Cgs variations, then the linearity improvement is enhanced, but the device area increases
Solution Approach 1:
The patent applies local quality by positioning the diode in a specific location within the amplifier structure where it can effectively compensate for Cgs variations. The diode is strategically placed with its anode at the gate and cathode at the drain, creating a localized compensation mechanism that targets the specific non-linearity issue without requiring extensive additional area throughout the entire device
Solution Approach 2:
The diode structure is nested within the existing amplifier footprint by utilizing the space between and around the FET components. The integrated diode shares the same physical structure and process fabrication as the FET, allowing the diode to be embedded within or adjacent to the FET structure rather than requiring separate dedicated space, thus achieving enhanced linearity compensation with minimal additional device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively compensates for the non-linear capacitance variations, enhancing the linearity of the amplifier by providing a sufficiently large non-linear capacitance between the gate and drain, thereby improving the overall performance of the FET MMIC chip power amplifier.
Implementation Method 1
the diode(C diode) providing an anode to cathode capacitance having the inverse non-linear relationship when the anode of the diode shares the gate node of the FET and the cathode of the diode share the drain node of the FET
Implementation Method 2
the diode's anode in Schottky contact with the gate and cathode in ohmic contact with the drain
Data Source
Figure 1~2
Figure 3A~3B
Figure 4A~4B
AI summary
A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.