FET Gate Current Shunting for Pre-Power Latch-Up Prevention

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Solution Overview

Problem

Transistor assemblies face issues with uncontrolled operation during a pre-power state due to disparities in power supply activation, leading to potential damage and safety concerns from uncontrolled current flow through gate-to-source capacitance.

Innovation Solution

Incorporation of a transistor assembly with gate current shunting capability, utilizing a capacitor and switching device to divert current away from the gate during the pre-power state, ensuring controlled operation and preventing FETs from turning on unexpectedly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FETs are used with high gate impedance and voltage control, then the device can be efficiently controlled, but during pre-power state with varying power supply voltage slopes, uncontrolled current flow occurs causing latch-up and damage

Engineering Contradiction:

Improvecircuit operation reliabilityVSAvoiduncontrolled current flow and latch-up risk

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A current shunting circuit comprising a shunting transistor and capacitor is introduced as an intermediary protective layer between the power supply and the FET gate. This mediator detects pre-power state conditions and actively shunts away harmful current flows that would otherwise reach the FET gate, preventing latch-up while not interfering with normal FET operation during powered state

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective circuit performs preliminary detection of pre-power state conditions before they can cause damage. By monitoring the voltage slope and state of power supplies in advance, the circuit proactively activates the shunting mechanism to counteract potential harmful effects before they manifest as latch-up or damage to the FET

Inventive Principle:

Principle #9Preliminary anti-action

2Ease of operation

If the gate-to-source threshold voltage is low to enable easier switching, then the FET can be more easily controlled, but the risk of uncontrolled operation during pre-power state increases

Engineering Contradiction:

ImproveFET switching controlVSAvoidprotection against uncontrolled operation

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The shunting circuit acts as an intermediary gatekeeper that decouples the threshold voltage requirement from the protection mechanism. It allows the FET to maintain low threshold voltage for ease of control while the intermediary protective layer filters out harmful current paths during pre-power state, effectively separating the switching function from the protection function

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If transistor assemblies include gate current shunting capability with capacitor and switching device, then uncontrolled current flow is prevented, but the device complexity increases

Engineering Contradiction:

Improveprotection against latch-upVSAvoidtransistor assembly structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The shunting transistor and capacitor are designed to serve multiple functions: detecting pre-power state conditions, shunting harmful currents, and automatically deactivating when normal operation begins. This multi-functionality reduces the need for separate protective components and control logic, thereby minimizing the increase in device complexity while achieving comprehensive protection

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes uncontrolled current flow, preventing FETs from operating in their on-state during the pre-power phase, thereby reducing the risk of damage and ensuring stable circuit operation.

Implementation Method 1

charging a gate-to-source capacitance of a second N-channel field effect transistor (FET) via a capacitor

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

shunting current away from a gate of a first N-channel field effect transistor (FET) via the second N-channel FET

Methodology Applied

Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS12574025B2Transistor assemblies with gate current shunting capability, and associated methods

Publication Date: 2026.03.10 ANALOG DEVICES INC

AI summary

A transistor assembly with gate current shunting capability includes first field effect transistor (FET), a first pull-up current source, a first pull-down current source, a first switching device, a control circuit, a capacitor, and a second FET. The first FET is an N-channel FET including a first gate, a first drain, and a first source. The first drain is electrically coupled to a first power supply. Each of the pull-up current source and the pull-down current source is electrically coupled to the first gate. The first switching device is electrically coupled in series with the first pull-down current source and is controlled by a first control signal. The control circuit is at least partially powered by a second power supply and generates the first control signal. The capacitor and the second FET collectively shunt current away from the first gate during a pre-power operating state of the transistor assembly.