Gate Cut Process for Field Effect Transistors
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Solution Overview
Problem
Conventional methods for forming field effect transistors (FETs) are limited in increasing device density due to requirements for minimum gate-to-gate and semiconductor body-to-semiconductor body spacing to avoid processing-induced shorting.
Innovation Solution
A gate cut process is employed following final gate formation to form isolation regions between gates and semiconductor bodies, allowing for reduced spacing and increased device density by segmenting elongated gates and semiconductor bodies using isolation layers and dopant implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods of forming FETs are used with fixed minimum gate-to-gate spacing, then processing-induced shorting between gates is avoided, but device density increases are limited
Solution Approach 1:
The patent applies segmentation by dividing a single continuous gate structure into multiple separate gates using isolation regions. This is achieved by forming isolation regions that extend through the gate conductor layer, physically segmenting the gate into discrete sections. This segmentation allows adjacent gates to be positioned closer together without causing shorting, as the isolation regions prevent electrical connection between adjacent gate structures, thereby resolving the contradiction between maintaining reliability and increasing device density
Solution Approach 2:
The patent uses isolation regions as intermediary structures between adjacent gates. These isolation regions, formed by depositing dielectric material and extending through the gate conductor layer, act as mediators that electrically isolate adjacent gates from each other. This intermediary structure enables reduced gate-to-gate spacing while preventing processing-induced shorting, thus resolving the technical contradiction between improving device density and maintaining reliability
2Reliability
If adjacent semiconductor bodies are spaced at fixed minimum predetermined distance, then shorting is avoided, but device density increases are limited
Solution Approach 1:
The patent applies segmentation by dividing a single continuous semiconductor body into multiple separate semiconductor bodies using isolation regions. The isolation regions extend through the semiconductor body, physically segmenting it into discrete sections. This segmentation allows adjacent semiconductor bodies to be positioned closer together without causing shorting, as the isolation regions prevent electrical connection between adjacent semiconductor body sections, thereby resolving the contradiction between maintaining reliability and increasing device density
Data Source
AI summary
Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.