Field-Effect Transistor Gate Stack With Interfacial Dipole Tuning
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Solution Overview
Problem
The challenge in fabricating field-effect transistors, such as FinFETs, lies in modulating threshold voltage while dealing with reduced feature sizes, as directly patterning work function metal layers is limited due to merged metal films, and directly patterning gate dielectric layers is hindered by thermal-driven instability.
Innovation Solution
The method involves forming a high-k metal gate structure by removing a dummy gate structure, depositing a high-k dielectric layer, and using alternating cycles of metal-containing and aluminum-containing precursors to create a metal oxide layer at the interface, facilitating Al atom diffusion and forming aluminum oxide, which introduces dipole moments to modulate the threshold voltage without requiring high-temperature thermal treatments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If directly patterning work function metal layers is used to modulate threshold voltage, then threshold voltage control is achieved, but the process becomes limited due to merged metal films at reduced feature sizes
Solution Approach 1:
The patent introduces an intermediary aluminum oxide layer formed between the high-k dielectric and the work function metal layer. This intermediate layer serves as a mediator to modulate threshold voltage through its dipole moment, eliminating the need for direct patterning of work function metal layers. The aluminum oxide layer is deposited conformally and then selectively removed in non-patterning steps, avoiding the merged metal films problem that occurs at reduced feature sizes.
2Manufacturing precision
If directly patterning gate dielectric layers is used to modulate threshold voltage, then threshold voltage control is achieved, but thermal-driven instability occurs during fabrication
Solution Approach 1:
The patent uses an aluminum oxide intermediary layer deposited conformally over the high-k dielectric layer. This intermediate layer protects the gate dielectric from direct exposure to high-temperature thermal processing, preventing thermal-driven instability. The aluminum oxide layer can be selectively removed later through non-patterning methods such as selective etching or sacrificial layer removal, avoiding the need to directly pattern the gate dielectric layer.
Solution Approach 2:
The patent performs preliminary deposition of the aluminum oxide layer before subsequent high-temperature processing steps. This preliminary action creates a protective barrier that prevents thermal damage to the gate dielectric during later fabrication steps. The aluminum oxide layer is then selectively removed through non-patterning methods, achieving threshold voltage modulation without directly patterning the thermally sensitive gate dielectric.
3Reliability
If metal gate structure is formed by replacing dummy polysilicon gate after other components are fabricated, then device performance is improved, but the fabrication process complexity increases at reduced feature sizes
Solution Approach 1:
The patent performs preliminary deposition of the high-k dielectric layer and aluminum oxide intermediary layer on the dummy gate structure before removing the dummy gate. This preliminary action allows the metal gate structure to be formed with precise control over the gate dielectric and intermediary layer, improving device performance. The sequential deposition and selective removal steps are integrated into the existing fabrication flow, managing process complexity at reduced feature sizes.
Solution Approach 2:
The patent segments the gate structure formation into distinct steps: depositing high-k dielectric over dummy gate, depositing aluminum oxide intermediary layer, removing dummy gate, and forming metal gate. This segmentation allows each step to be optimized independently, improving overall device performance while managing fabrication complexity through systematic process breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively tunes the threshold voltage of the metal gate structure, enhancing device performance by increasing the work function without the complexity of patterning work function metal layers and enabling fabrication at reduced length scales.
Implementation Method 1
facilitating Al atom diffusion and forming aluminum oxide
Implementation Method 2
applying alternating cycles of metal-containing and aluminum-containing precursors to create a metal oxide layer at the interface
Implementation Method 3
forming aluminum oxide, which introduces dipole moments to modulate the threshold voltage
Data Source
AI summary
A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.