FET Gate-Drain Short Detection Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional switching circuits lack a mechanism to detect and prevent thermal events caused by gate-drain shorts in field effect transistors (FETs), which can lead to device failure and system malfunctions due to the absence of a method to notify the system of such failures.
Innovation Solution
A diagnostic circuit and method that floats the FET gate during a test period and compares the output voltage to a threshold voltage, signaling a fault if exceeded, and applies containment measures to prevent thermal events by setting a serial protocol interface flag or using an anti-fuse to prevent sleep mode activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the FET gate is allowed to float during sleep mode, then the FET can enter low-power state, but the resistive gate-drain short causes the floating gate voltage to rise toward the supply voltage, causing the FET to become partially enhanced and operate in the linear region, dissipating large amounts of heat
Solution Approach 1:
The diagnostic circuit performs a gate-drain short detection test before the FET enters sleep mode by measuring the gate voltage while the gate is still controlled. If a short is detected, the system prevents the FET from entering sleep mode or takes containment actions, thereby avoiding the harmful thermal event that would occur if the gate were allowed to float with an existing short
Solution Approach 2:
The system implements a feedback mechanism where the diagnostic circuit continuously monitors the FET for gate-drain shorts and provides status information to the control logic. This feedback enables the system to adjust its operation - preventing sleep mode entry or triggering containment - based on the detected fault condition, thus avoiding the thermal event while maintaining low-power operation when healthy
2Reliability
If no detection mechanism is implemented, then the device complexity remains low, but there is no way to notify the system of a switching circuit failure caused by a gate-drain short, and no way to prevent the failure from progressing into a thermal event
Solution Approach 1:
The patent introduces a separate diagnostic circuit as an intermediary component that specifically tests for gate-drain shorts. This mediator circuit measures the gate voltage during a test period and compares it to a threshold, providing fault detection capability without requiring fundamental changes to the main FET switching circuitry, thus adding only minimal complexity while significantly improving reliability
Solution Approach 2:
The diagnostic circuit performs detection during a test period before normal operation begins or before sleep mode is entered. By conducting the measurement in advance, the system can identify potential failures before they progress to thermal events, achieving high reliability through proactive detection rather than reactive response
3Power
If the FET operates in the linear region due to gate-drain short, then the FET can dissipate large amounts of heat, but this leads to a destructive thermal event
Solution Approach 1:
The system applies preliminary anti-action by detecting the gate-drain short condition and preventing the FET from entering the problematic sleep mode state where the gate would float and cause linear region operation. The containment logic actively counteracts the potential harmful effect by adjusting operating conditions or disabling the FET before excessive power dissipation and thermal events can occur
Data Source
AI summary
A fault diagnostic circuit (100) and associated method of operation are described for testing an FET device (114) for a gate-drain short failure (113) by floating the FET gate during a predetermined test period and then comparing (118) the FET output voltage (115) at the source to a predetermined threshold voltage (VTHRESHOLD) which may be selected as a percentage of the power supply voltage (VPOWER) for the FET device to determine if the FET output voltage is greater than the threshold voltage, in which case a device fault is signaled (119).