FET Gate Drive Circuit With Delayed Pulse Voltage Hold
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Solution Overview
Problem
Drive circuits that use field effect transistors to control devices often experience a drop in voltage when a pulse signal is delayed, leading to inadequate timing in driving the controlled device.
Innovation Solution
A drive circuit configuration that includes a drive signal output circuit, a switching circuit with static capacitance to maintain voltage, a delay circuit to manage the switching element's state, and a reverse flow suppressing unit to prevent current reversal, ensuring stable voltage delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a delay circuit is used to delay the input of a pulse signal to the gate terminal, then the timing control is improved, but the voltage of the pulse signal drops
Solution Approach 1:
The circuit performs preliminary charging of the capacitor C1 before the delay operation. By pre-charging the capacitor to a voltage higher than the power supply voltage Vcc, the circuit ensures that even after voltage drop during delay, the gate voltage remains sufficient to maintain proper switching operation of the field effect transistor.
Solution Approach 2:
The circuit changes the voltage parameter of the capacitor C1 to be higher than the normal power supply voltage Vcc. This parameter change allows the capacitor to provide a voltage buffer that compensates for voltage drops during the delay period, ensuring stable operation despite the time delay introduced by the delay circuit.
2Loss of time
If the switching element switches between on and off states for delay, then the timing delay is achieved, but current may flow in reverse direction causing voltage instability
Solution Approach 1:
The diode D1, which prevents reverse current flow, converts the potential harmful reverse current into a beneficial unidirectional current flow. By blocking reverse current from the capacitor C1 to the delay circuit, the diode ensures that the capacitor discharges only in the forward direction through the switching element, maintaining voltage stability and preventing oscillations during the delay period.
3Power
If the capacitor charges to high voltage for delay compensation, then voltage drop is prevented, but energy is consumed in charging and maintaining the capacitor
Solution Approach 1:
The charging of capacitor C1 is performed periodically through the charging circuit rather than continuously. The capacitor is charged to a higher voltage level during specific charging phases and then maintains this voltage during the delay operation, reducing overall energy consumption compared to continuous charging while still preventing voltage drop during the delay period.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed drive circuit effectively inhibits voltage drops, allowing for precise timing in switching the field effect transistor, preventing missed pulses and ensuring proper device operation.
Implementation Method 1
a holding a static capacitance for applying a voltage corresponding to an accumulated electric charge to a signal terminal of the switching element
Data Source
AI summary
A drive circuit capable of inhibiting a drop of a voltage of a drive signal is provided. A drive circuit includes: a drive signal output circuit configured to output a pulse signal input to a gate terminal of a first field effect transistor driving a device; a switching circuit having a switching element that is connected between the gate terminal and the signal output terminal and configured to switch a conduction state between the gate terminal and output terminal; a delay circuit configured to delay an input of the drive signal to the gate terminal by switching a state of the switching element between an on state and an off state; and a reverse flow suppressing unit configured to suppress a reverse flow of a current from the static capacitance to the drive signal output circuit.