FET Gate End Trimming for Reduced Edge Capacitance
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Solution Overview
Problem
Existing semiconductor fabrication methods result in significant gate material extending past the active region of field-effect transistors (FETs), leading to increased edge capacitance that degrades FET performance.
Innovation Solution
The FET device design includes a gate that extends across the active region, with at least one end extending past the corresponding edge of the active region by a sub-lithographic dimension, achieved through cyclic metal oxidation and etching, and the formation of spacers in trenches at the gate ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate is extended past the active region using conventional lithography, then the gate coverage is improved, but the gate edge capacitance increases and FET performance degrades
Solution Approach 1:
The gate is preliminarily extended beyond the desired final position to allow subsequent processing steps (trench formation, cyclic oxidation, etching, spacer deposition) to achieve the precise sub-lithographic extension. This preliminary over-extension enables the use of self-aligned processes that achieve precision unattainable by lithography alone.
Solution Approach 2:
The patent replaces conventional lithographic patterning (optical/mechanical system) with a sequence of chemical and physical vapor deposition processes (cyclic oxidation, etching, spacer formation) to achieve the gate extension. This substitution enables sub-lithographic precision by using self-aligned atomic-layer processes instead of optical diffraction-limited patterning.
2Object-affected harmful factors
If cyclic metal oxidation and etching is performed to reduce gate extension, then edge capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The gate extension reduction is achieved through segmentation of the manufacturing process into discrete cyclic steps: oxidation, etching, spacer deposition, and removal. Each cycle removes a small portion of the gate extension, and multiple cycles are performed to achieve the desired sub-lithographic dimension. This segmentation transforms a single complex etching operation into multiple controlled, self-aligned steps.
Solution Approach 2:
The patent employs periodic cyclic action where the oxidation-etching-spacer formation sequence is repeated multiple times. Each cycle progressively reduces the gate extension by a controlled amount. The periodic repetition of these self-aligned cycles enables precise control over the final gate dimension while maintaining process control and consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the gate material extending past the active region to sub-lithographic dimensions, thereby reducing edge capacitance and improving FET performance.
Implementation Method 1
performing cyclic metal oxidation and etching to reform the end of the gate increasingly inwardly toward a corresponding edge of the active region
Implementation Method 2
performing cyclic metal oxidation and etching to reform the end of the gate increasingly inwardly toward a corresponding edge of the active region
Data Source
AI summary
A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corresponding edge of the active region by a sub-lithographic dimension.