FET Transistor Gate Pattern Etching Thickness Control
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Solution Overview
Problem
Current methods for producing nanoscale field effect transistors (FETs) suffer from significant local dispersion in semiconductor thickness, leading to reduced yield and non-uniform electrical performance due to uncontrolled etching and thickness fluctuations in the channel and source/drain zones, which affects the functionality of integrated circuits.
Innovation Solution
A method involving photolithography to define a gate pattern in a protective oxide layer, followed by controlled etching to maintain the initial thickness of the semiconductor layer for both channel and source/drain zones, ensuring uniformity and preventing over-etching, while forming spacers integrally with slanted walls to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uncontrolled etching is performed to define the gate pattern, then the gate structure can be formed, but the semiconductor layer thickness becomes non-uniform and locally dispersed
Solution Approach 1:
A protective layer is formed on the semiconductor layer before gate pattern definition. This protective layer serves as an etch stop layer that prevents over-etching and maintains uniform thickness of the semiconductor layer in source/drain zones while allowing gate pattern formation through the protective layer.
Solution Approach 2:
The protective layer acts as an intermediary between the etching process and the semiconductor layer. It absorbs the etching action, protecting the semiconductor layer from direct etching damage and thickness variation, while still allowing the gate pattern to be defined through selective etching of the protective layer.
2Reliability
If the semiconductor layer thickness is reduced to achieve thin channel FDSOI transistors, then electrostatic control is improved, but the layer becomes vulnerable to complete etching and thickness fluctuations
Solution Approach 1:
The protective layer is deposited on the thin semiconductor layer before any etching operations. This preliminary protective action ensures that even when the semiconductor layer is very thin (for good electrostatic control), it will not be completely etched away and will maintain controlled thickness throughout the manufacturing process.
Solution Approach 2:
The protective layer provides a cushioning effect against the etching process. It acts as a buffer that prevents the etching from reaching and removing the entire thin semiconductor layer, thereby cushioning the thin layer against complete removal and maintaining its thickness for reliable electrostatic control.
3Device complexity
If multiple etching steps are performed to define gate and spacers, then the transistor structure is complete, but the semiconductor thickness varies significantly across the wafer
Solution Approach 1:
The protective layer is formed once before the series of etching steps. This single preliminary protective action covers all subsequent etching operations (gate definition, spacer formation, etc.), ensuring that the semiconductor layer thickness remains uniform across the wafer despite multiple processing steps.
Solution Approach 2:
The protective layer serves as a continuous intermediary throughout multiple etching steps. It mediates between all etching processes and the semiconductor layer, preventing thickness variation accumulation that would otherwise occur with multiple direct etching operations on the thin semiconductor layer.
4Reliability
If the semiconductor layer is thinned to nanometric dimensions, then short channel effects are reduced, but local dispersion and yield reduction occur
Solution Approach 1:
The protective layer is deposited before any thinning or etching operations. This ensures that the semiconductor layer can be thinned to the required nanometric dimensions for good short channel effect control, while the protective layer prevents local dispersion and complete removal, thereby maintaining high wafer yield.
Solution Approach 2:
The protective layer provides beforehand cushioning that enables the semiconductor layer to be thinned to nanometric dimensions with confidence. It cushions against local variations and complete etching, allowing aggressive thinning for short channel control while maintaining productivity through high yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent thickness across all transistors on a wafer, improving yield and electrical performance by minimizing thickness variations and reducing parasitic capacitance, thus enhancing the reliability of nanoscale FETs for advanced technological nodes.
Implementation Method 1
defining, by photolithography, a gate pattern in the protective layer
Implementation Method 2
etching the gate pattern into the superficial layer so as to leave a controlled thickness of the layer of semiconductor material in place
Implementation Method 3
The RSDs 112 are formed by local epitaxy of these zones from the superficial layer 132 of the SOI
Data Source
AI summary
A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.