FET Gate Insulation via Catalytic CVD Silicon Nitride
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Solution Overview
Problem
Field-effect transistors used in high-frequency bands face challenges with moisture resistance, leading to increased costs due to the need for airtight packaging and thicker moisture-resistant insulating films, which can deteriorate device characteristics by increasing gate capacitance and reducing gain.
Innovation Solution
A field-effect transistor design featuring a T-shaped or Γ-shaped gate electrode with a cavity formed by a thick silicon nitride film deposited using catalytic CVD, reducing the number of manufacturing steps and maintaining moisture resistance while minimizing gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick moisture-resistant insulating film is used to enhance moisture resistance, then moisture resistance is improved, but gate capacitance increases and device characteristics deteriorate
Solution Approach 1:
The insulating film is segmented into two distinct layers: a first insulating film (thick, 50-200 nm) providing moisture resistance, and a second insulating film (thin, 5-50 nm) with low dielectric constant placed between the gate electrode and semiconductor layer to minimize gate capacitance. This segmentation allows each layer to fulfill its specific function independently.
Solution Approach 2:
Different regions of the insulating structure are assigned different material properties: the first insulating film uses high moisture resistance materials (SiO2, Si3N4, SiOxNy) while the second insulating film uses low dielectric constant materials (SiO2, SiC, SiON) to optimize local electrical characteristics where needed.
2Reliability
If an airtight package is used to protect the transistor, then moisture resistance is improved, but manufacturing cost increases
Solution Approach 1:
The moisture protection function is extracted from the packaging system and integrated directly into the semiconductor device structure through the dual-layer insulating film system. This eliminates or reduces the need for expensive airtight packaging while maintaining moisture resistance.
Solution Approach 2:
The invention uses standard semiconductor fabrication processes and common insulating materials that are already part of the manufacturing workflow, avoiding the need for specialized expensive packaging solutions. The insulating films are formed using conventional CVD or spin-coating techniques.
3Reliability
If multiple process steps are used to form cavity and laminate films, then moisture resistance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The first insulating film is formed preliminarily as a thick moisture-resistant layer before the gate electrode is fully processed. Subsequently, the second insulating film is added on top, creating the complete moisture protection system as an integrated part of the gate structure formation process rather than as separate post-processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces manufacturing costs and maintains moisture resistance, effectively lowering gate capacitance and improving device performance by eliminating the need for additional process steps and airtight packaging.
Implementation Method 1
a silicon nitride film deposited by catalytic CVD for covering the insulating film
Data Source
AI summary
A low-cost field-effect transistor with a moisture-resistant gate covered by a thick moisture-resistant insulating film which suppresses an increase in gate capacitance, and a method of manufacturing the field-effect transistor. The field-effect transistor has one of a T-shaped gate electrode and Γ-shaped gate electrode, a drain electrode, and a source electrode, the source electrode and the drain electrode being electrically connected through an n-doped semiconductor region. The gate, source, and drain electrodes are located on a semiconductor layer which includes an insulating film having a thickness of 50 nm or less and covering a surface of the gate electrode and a surface of the semiconductor layer. A silicon nitride film, deposited by catalytic CVD, covers the insulating film and includes a void volume located between a portion of the gate electrode corresponding to a canopy of an open umbrella and the semiconductor layer.