FET Gate Stack Segmentation to Block La Diffusion
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Solution Overview
Problem
As integrated circuits downscale, transistors with higher drive currents are needed, leading to challenges in manufacturing three-dimensional field-effect transistors (FETs) where ion implantation processes require careful geometrical management to prevent threshold voltage shifts due to process and structural issues.
Innovation Solution
The semiconductor device incorporates a gate stack structure with an interfacial layer, gate dielectric layer, conductive layers, work function adjustment material layers, and a body gate electrode layer, which helps in preventing La diffusion across the boundary of different threshold voltage devices by using a WFM layer and a glue layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device spacing is decreased to increase integration density, then productivity is improved, but threshold voltage stability deteriorates due to La diffusion between adjacent devices
Solution Approach 1:
A glue layer is introduced as an intermediary barrier between adjacent FET devices to prevent La diffusion. This glue layer acts as a diffusion barrier that blocks the movement of La atoms from the gate dielectric of one device to the gate dielectric of an adjacent device, thereby maintaining threshold voltage stability while allowing reduced device spacing for higher integration density
Solution Approach 2:
The gate dielectric layer is segmented into multiple regions corresponding to different FET devices, with each region having controlled La doping. The glue layer creates clear segmentation boundaries between these doped regions, preventing cross-contamination of La atoms between adjacent device regions while maintaining the desired doping profiles within each device
2Reliability
If ion implantation is used to adjust threshold voltage, then device performance is improved, but geometric precision requirements increase due to sensitivity to process variations
Solution Approach 1:
Instead of relying on precise ion implantation geometry, the patent changes the approach by controlling La concentration through deposition parameters and using the glue layer as a diffusion barrier. This parameter-based control method reduces sensitivity to geometric variations in the ion implantation process while achieving the desired threshold voltage adjustment
3Reliability
If La is added to gate dielectric to adjust threshold voltage, then device performance is improved, but La diffusion to adjacent devices occurs causing threshold voltage shifts
Solution Approach 1:
The glue layer serves as an intermediary diffusion barrier that allows each FET device to have its own La-doped gate dielectric region without La atoms diffusing into adjacent devices. This mediator structure enables independent threshold voltage control for each device while preventing the harmful cross-diffusion effect
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses La diffusion, preventing threshold voltage shifts and enhancing the reliability and performance of FETs in scaled-down integrated circuits.
Implementation Method 1
a diffusion barrier is formed by filling the trench with a dielectric material or a conductive material. At least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, and a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer
Data Source
AI summary
A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.