FET Gate Reset Circuit for Faster High-Power Switching
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Solution Overview
Problem
High-speed switches used in applications like transceivers face increased switching times due to parasitic capacitance from stacked field effect transistors, which hinder their ability to handle high power signals efficiently.
Innovation Solution
Implementing a reset circuit that couples the gate of the FET to a reference potential during a reset period to minimize charge accumulation, thereby reducing the load on the power supply and accelerating switching time by disconnecting the driver from the gate and reconnecting it only after the gate is reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If stacked FETs are used to increase power handling capability, then power handling capability is improved, but switching time increases due to parasitic capacitance
Solution Approach 1:
The gate is reset to a reference potential (ground) before the actual switching operation. This preliminary reset action removes accumulated charge from the gate, reducing parasitic capacitance effects and enabling faster subsequent switching while maintaining the power handling capability provided by the stacked FET configuration
Solution Approach 2:
The switching operation is divided into two distinct phases: a reset phase where the gate is coupled to reference potential to clear charge, and a switching phase where the driver controls the gate. This segmentation allows the system to benefit from both fast switching (by starting from a known low-capacitance state) and high power handling (through the stacked FET structure)
2Power
If gate charge is accumulated to maintain FET conduction, then power handling is maintained, but load on power supply increases and switching speed decreases
Solution Approach 1:
The gate undergoes periodic resetting to reference potential at the end of each conduction period. This periodic action removes accumulated charge that would otherwise increase parasitic capacitance and slow down subsequent switching operations, thereby maintaining high switching speed while allowing the FET to conduct at full power during its active period
3Ease of operation
If driver output is continuously connected to gate, then FET remains controllable, but charge accumulation increases parasitic capacitance and slows switching
Solution Approach 1:
The driver output is temporarily disconnected from the gate during the reset period. This extraction of the driver connection allows the gate to be reset to reference potential without interference, removing accumulated charge and reducing parasitic capacitance. After resetting, the driver reconnects to the gate to resume control, achieving both fast switching and maintained controllability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces switching time and voltage source settling time by minimizing the loading effect on the power supply, allowing for faster transitions between switch states.
Implementation Method 1
increased the parasitic capacitance of the gates when the FETs are stacked results in an increase in switching time
Data Source
AI summary
A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.