FET Gate Fabrication with Schottky Metal Intermediary
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for fabricating field effect transistor gates, such as the dielectric-assisted T-gate process, suffer from surface damage and dimensional inaccuracies due to dry etching, leading to increased leakage current and reduced reliability, while separate gate and field plate approaches result in inferior performance due to spacing issues and external connections.
Innovation Solution
A method involving the deposition of a thin Schottky metal layer on the semiconductor surface before dielectric deposition, followed by dry etching that stops at the metal layer, which protects the surface and maintains dimensional accuracy, allowing for an integrated gate and field plate structure with improved control over gate length and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dry etching is used to define the gate through the dielectric layer, then the gate structure can be formed, but surface damage and dimensional inaccuracies occur leading to increased leakage current
Solution Approach 1:
A sacrificial metal layer is introduced as an intermediary between the dielectric layer and the semiconductor substrate. This sacrificial layer serves as a protective mediator during dry etching, preventing direct damage to the semiconductor surface while allowing the gate structure to be formed through the dielectric layer.
Solution Approach 2:
The sacrificial metal layer is deposited beforehand to cushion and absorb the damaging effects of dry etching on the semiconductor substrate. This pre-positioned protective layer prevents surface damage and dimensional inaccuracies before they can affect the final device performance.
2Ease of manufacture
If separate gate and field plate approaches are used, then fabrication flexibility is improved, but performance deteriorates due to spacing issues and external connections
Solution Approach 1:
The gate and field plate are merged into a single integrated structure formed in one lithography and deposition step. The sacrificial metal layer enables this merging by providing a continuous underlying layer that allows both structures to be formed simultaneously without spacing issues or external connections.
3Ease of manufacture
If the gate is defined by dry etching through dielectric, then manufacturing is simplified, but manufacturing precision deteriorates due to dimensional inaccuracies
Solution Approach 1:
The sacrificial metal layer acts as an intermediary reference plane during the gate definition process. It provides a stable, pre-defined dimensional reference that maintains manufacturing precision while simplifying the overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the power output and reliability of field effect transistors by minimizing damage and maintaining precise gate dimensions, resulting in lower gate leakage and improved device performance.
Implementation Method 1
depositing a gate metal layer on the thin Schottky metal layer
Implementation Method 2
defining a relatively thin Schottky metal gate by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface
Data Source
AI summary
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.