FET Gate Segmentation for Independent Threshold Tuning

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Solution Overview

Problem

Field effect transistor (FET) devices with connected nFET and pFET gates face challenges in voltage characteristics due to shared fabrication, making it difficult to independently tune the voltage thresholds of each device.

Innovation Solution

A field effect transistor device design that includes a dielectric layer on a substrate with separate metal layers and a boundary region, which electrically disconnects the nMOS and pMOS devices, allowing for independent tuning of voltage thresholds by forming a boundary region that separates the devices during fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If nFET and pFET gates are connected in fabrication, then manufacturing process is simplified, but voltage threshold tuning independence is lost

Engineering Contradiction:

Improvefabrication process simplicityVSAvoidvoltage threshold tuning independence

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The gate structure is segmented into nFET gate and pFET gate portions that are electrically isolated from each other. The conductive layer is divided into separate first and second portions, allowing independent voltage threshold tuning for each device type while maintaining a unified fabrication approach.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A dielectric layer is introduced as an intermediary between the nFET gate and pFET gate regions. This dielectric layer electrically isolates the two gate types, enabling independent voltage control while allowing both devices to be fabricated together in the same process.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If separate fabrication processes are used for nFET and pFET, then voltage threshold independence is achieved, but manufacturing complexity increases

Engineering Contradiction:

Improvevoltage threshold tuning independenceVSAvoidfabrication process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The fabrication processes for nFET and pFET are merged into a single unified process. Both device types are fabricated simultaneously in the same reactor using the same deposition and etching steps, reducing manufacturing complexity while maintaining gate independence through dielectric isolation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The conductive layer serves multiple functions: it forms both the nFET gate and pFET gate structures, and when separated by the dielectric layer, it enables independent voltage tuning for both device types within a single fabrication process.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If connected gates are used, then device area is reduced, but voltage characteristic control is compromised

Engineering Contradiction:

Improvedevice areaVSAvoidvoltage threshold control precision

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The electrical isolation between nFET and pFET gates is achieved in the vertical dimension by introducing a dielectric layer between the conductive gate portions, rather than requiring horizontal separation. This maintains compact device area while enabling precise independent voltage threshold control.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8742475B2Field effect transistor device and fabrication

Publication Date: 2014.06.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.